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公开(公告)号：US11188682B2
公开(公告)日：2021-11-30
申请号：US16378256
申请日：2019-04-08
Applicant: ARM Limited
Inventor： Bal S. Sandhu , George McNeil Lattimore , Carl Wayne Vineyard
Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.
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公开(公告)号：US11550965B2
公开(公告)日：2023-01-10
申请号：US16855659
申请日：2020-04-22
Applicant: Arm Limited
Inventor： Subbayya Chowdary Yanamadala , Jeremy Patrick Dubeuf , Carl Wayne Vineyard , Matthias Lothar Boettcher , Hugo John Martin Vincent , Shidhartha Das
Abstract: Analytics processing circuitry can include a data scavenger and a data analyzer coupled to receive the data from the data scavenger. The data scavenger collects data from at least one element of interest of a plurality of elements of interest of an IC. The data analyzer identifies patterns in the data from the data scavenger over a time frame or for a snapshot of time based on a predefined metric. The analytics processing circuitry can further include a moderator and a risk predictor. The risk predictor generates a risk assessment regarding whether the data collected by the data scavenger is indicative of normal behavior or abnormal behavior based at least on the output of the data analyzer and a behavioral model for the IC, which can be device and application specific. A threat response can be performed based on the risk assessment.
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公开(公告)号：US10924261B2
公开(公告)日：2021-02-16
申请号：US15600974
申请日：2017-05-22
Applicant: ARM Limited
Inventor： Robert John Harrison , Mikael Rien , Carl Wayne Vineyard , George Mcneil Lattimore , Christopher Neal Hinds , Adeline-Fleur Fleming
Abstract: An apparatus includes a power input, a power output, and a plurality of independent powering units each comprising at least one charge store. Each of the plurality of powering units is capable of receiving power from the power input while isolating the power output, and each of the plurality of powering units is capable of outputting power to the power output while isolating the power input.
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公开(公告)号：US20190236315A1
公开(公告)日：2019-08-01
申请号：US16378256
申请日：2019-04-08
Applicant: ARM Limited
Inventor： Bal S. Sandhu , George McNeil Lattimore , Carl Wayne Vineyard
CPC classification number: G06F21/755 , G06F1/28
Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.
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公开(公告)号：US10255462B2
公开(公告)日：2019-04-09
申请号：US15185789
申请日：2016-06-17
Applicant: ARM Limited
Inventor： Bal S. Sandhu , George McNeil Lattimore , Carl Wayne Vineyard
Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.
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Patent Agency Ranking
公开(公告)号：US11841943B2
公开(公告)日：2023-12-12
申请号：US16584865
申请日：2019-09-26
Applicant: Arm Limited
Inventor： Joshua Randall , Joel Thornton Irby , Carl Wayne Vineyard , Mudit Bhargava
IPC: G06F21/55 , G11C13/00 , H03K19/003
CPC classification number: G06F21/554 , G11C13/004 , G11C13/0069 , H03K19/003 , G06F2221/034
Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).
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公开(公告)号：US11822705B2
公开(公告)日：2023-11-21
申请号：US17536696
申请日：2021-11-29
Applicant: Arm Limited
Inventor： Bal S. Sandhu , George McNeil Lattimore , Carl Wayne Vineyard
CPC classification number: G06F21/755 , G06F1/28
Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.
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公开(公告)号：US11361111B2
公开(公告)日：2022-06-14
申请号：US16030459
申请日：2018-07-09
Applicant: Arm Limited
Inventor： Carl Wayne Vineyard , Christopher Neal Hinds , Adeline-Fleur Fleming
Abstract: A computing device incorporating repetitive side channel attack (SCA) countermeasures can include a timer circuit and a capacitive delay circuit that notifies of a potential repetitive-based attack by sending an activity-detected signal that can be used to initiate an appropriate countermeasure response. Additionally, or independently, a computing device incorporating repetitive SCA countermeasures can include at least one storage unit that can store an incoming input signal, at least one comparator to compare the incoming input signal with another signal and indicate a match, and a counter that increments upon the match. When the counter reaches a specified limit, a limit-exceeded signal can be sent to notify of a potential repetitive-based attack and initiate an appropriate countermeasure response.
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公开(公告)号：US20220083696A1
公开(公告)日：2022-03-17
申请号：US17536696
申请日：2021-11-29
Applicant: Arm Limited
Inventor： Bal S. Sandhu , George McNeil Lattimore , Carl Wayne Vineyard
Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.
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公开(公告)号：US09454313B2
公开(公告)日：2016-09-27
申请号：US14300735
申请日：2014-06-10
Applicant: ARM Limited
Inventor： Christopher Neal Hinds , Steven D. Krueger , Carl Wayne Vineyard
CPC classification number: G06F3/0617 , G06F3/0658 , G06F3/0659 , G06F3/0673 , G06F9/467 , G06F13/1663
Abstract: A data processing system includes a memory controller which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.
Abstract translation: 数据处理系统包括存储器控制器，其从多个候选管理算法中动态地选择要用于管理存储器访问冲突的所选择的管理算法。 存储器管理算法可以包括使用存储器锁的推测存储器访问问题和/或存储器访问问题的各种版本。 基于检测到的系统状态参数进行动态选择。 这些检测到的状态参数可以包括冲突级指示符，诸如在全局，每进程，每区域或每个线程的一个或多个上跟踪的存储器访问冲突计数器。
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