公开(公告)号：US10788886B2

公开(公告)日：2020-09-29

申请号：US15567707

申请日：2016-03-16

Applicant: ARM LIMITED

Inventor： Dominic William Brown ,  Christopher Vincent Severino ,  Ashley John Crawford

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3215

Abstract: A data processing apparatus has a number of devices having a normal state and a quiescent state in which the device is ready for being placed in a power saving state. Each device provides at least one preference indication indicative of a preference to operate in the normal state or the quiescent state. A controller controls a common state transition process for transitioning each of the devices 4 between the normal state and the quiescent state based on the preference indication received from each device.

公开(公告)号：US20170269657A1

公开(公告)日：2017-09-21

申请号：US15462146

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Dominic William Brown ,  Ashley John Crawford ,  Christopher Vincent Severino

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F1/3287 ,  G06F13/1689 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

Abstract: Various implementations described herein are directed to a method and apparatus for a low power interface combiner for controlling a cross domain component in a system of two or more power domain controls. The combiner may include a first state for requesting cross domain component quiescence when a first control requests quiescence and a second state for ensuring cross domain component quiescence before accepting the first control quiescence request. The combiner may include a third state for requesting cross domain component quiescence exit when a last control requests quiescence exit and other controls have exited or are exiting quiescence. The combiner may include a fourth state for ensuring cross domain component quiescence exit before accepting the last control quiescence exit request.