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公开(公告)号：US20180210805A1
公开(公告)日：2018-07-26
申请号：US15838615
申请日：2017-12-12
Applicant: ARM Limited
CPC classification number: G06F11/3466 , G06F7/548 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F11/141 , G06F11/3471 , G06F11/3476
Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry. An apparatus has an input interface to receive execution information from the processing circuitry indicative of operations performed by that processing circuitry when executing a sequence of instructions. The sequence includes at least one predicated vector memory access instruction executed to perform a memory transfer operation in order to transfer data values of a vector between a vector register and addresses accessed in memory. The vector comprises a plurality of lanes, where the number of lanes is dependent on the size of the data values represented within the vector, and predicate information referenced when executing the predicated vector memory access instruction is used to determine which lanes are subjected to the memory transfer operation. The apparatus has trace generation circuitry to generate from the execution information a data trace stream comprising a plurality of trace elements. For each predicated vector memory access instruction executed, the trace generation circuitry is arranged to issue within the data trace stream a number of address trace elements, each address trace element providing an address indication for an address accessed in memory, and each address trace element being associated with a fixed sized data block irrespective of the size of the data values accessed when executing the memory access instruction. The trace generation circuitry further issues within the data trace stream, for each predicated vector memory access instruction executed, at least one predicate trace element to identify any lanes of the vector that have been omitted from the memory transfer operation. It has been found that such an approach provides a particularly bandwidth efficient mechanism for tracing predicated vector memory access instructions.
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公开(公告)号：US12174755B2
公开(公告)日：2024-12-24
申请号：US18247400
申请日：2021-08-11
Applicant: Arm Limited
Abstract: An apparatus and method for constraining access to memory using capabilities. Processing circuitry performs operations during which access requests to memory are generated, with memory addresses for the access requests being generated using capabilities that identify constraining information. Capability checking circuitry performs a capability check operation to determine whether a given access request whose memory address is generated using a given capability is permitted based on the constraining information. Memory access checking circuitry then further constrains access to the memory by the given access request in dependence on a level of trust. The given capability has a capability level of trust associated therewith, and the level of trust associated with the given access request is dependent on both the current mode level of trust associated with the current mode of operation of the processing circuitry, and the capability level of trust of the given capability.
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公开(公告)号：US11704127B2
公开(公告)日：2023-07-18
申请号：US16628418
申请日：2018-06-19
Applicant: ARM LIMITED
CPC classification number: G06F9/30043 , G06F9/3013 , G06F9/30189 , G06F9/461
Abstract: A data processing system includes processing circuitry for executing context-data-dependent program instructions which are decoded by decoder circuitry. Such context-data-dependent program instructions perform processing which is dependent upon currently existing context data. As an example, the context-data-dependent program instructions may be floating point instructions and the context data may be rounding mode information. The decoder circuitry supports a context save instruction which saves context data when it is marked as having been used and saves default context data when the current context data is marked as not having been used. The decoder circuitry further supports a context restore instruction which restores context data when the current context data is marked as having been used and permits the current context data to continue for future use when it is marked as currently unused.
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公开(公告)号：US11609863B2
公开(公告)日：2023-03-21
申请号：US16975255
申请日：2020-06-24
Applicant: Arm Limited
IPC: G06F12/14 , G06F12/02 , G06F12/1009
Abstract: An apparatus comprises capability checking circuitry 86 to perform a capability validity checking operation to determine whether use of a capability satisfies one or more use-limiting conditions. The capability comprises a pointer and pointer-use-limiting information specifying the one or more use-limiting conditions. The one or more use-limiting conditions comprise at least an allowable range of addresses for the pointer. In response to a capability write request requesting that a capability is written to a memory location associated with a capability write target address, when capability write address tracking is enabled, capability write address tracking circuitry 200 updates a capability write address tracking structure 100 based on the capability write target address.
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公开(公告)号：US11550735B1
公开(公告)日：2023-01-10
申请号：US17486639
申请日：2021-09-27
Applicant: Arm Limited
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , Jack William Derek Andrew
Abstract: Memory access control circuitry controls handling of a memory access request based on at least one memory access control attribute associated with a region of address space including the target address. The memory access control circuitry comprises: lookup circuitry comprising a plurality of sets of comparison circuitry, each set of comparison circuitry to detect, based on at least one address-region-indicating parameter associated with a corresponding region of address space, whether the target address is within the corresponding region of address space; region mismatch prediction circuitry to provide a region mismatch prediction indicative of which of the sets of comparison circuitry is predicted to detect a region mismatch condition; and comparison disabling circuitry to disable at least one of the sets of comparison circuitry that is predicted by the region mismatch prediction circuitry to detect the region mismatch condition for the target address.
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Patent Agency Ranking
公开(公告)号：US10768938B2
公开(公告)日：2020-09-08
申请号：US16085053
申请日：2017-03-21
Applicant: ARM Limited
Inventor： Thomas Christopher Grocutt , Richard Roy Grisenthwaite , Simon John Craske , François Christopher Jacques Botman , Bradley John Smith
Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.
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公开(公告)号：US20250156182A1
公开(公告)日：2025-05-15
申请号：US18835476
申请日：2022-12-20
Applicant: Arm Limited
IPC: G06F9/30
Abstract: An apparatus is described having processing circuitry to perform vector processing operations, a set of vector registers, and an instruction decoder to decode vector instructions to control the processing circuitry to perform the required operations. The instruction decoder is responsive to a given vector memory access instruction specifying a plurality of memory access operations, where each memory access operation is to be performed to access an associated data element, to determine, from a data vector indication field of the given vector memory access instruction, at least one vector register in the set of vector registers associated with a plurality of data elements, and to determine, from at least one capability vector indication field of the given vector memory access instruction, a plurality of vector registers in the set of vector registers containing a plurality of capabilities. Each capability is associated with one of the data elements in the plurality of data elements and provides an address indication and constraining information constraining use of that address indication when accessing memory. The number of vector registers determined from the at least one capability vector indication field is greater than the number of vector registers determined from the data vector indication field. The instruction decoder controls the processing circuitry: to determine, for each given data element in the plurality of data elements, a memory address based on the address indication provided by the associated capability, and to determine whether the memory access operation to be used to access the given data element is allowed in respect of that determined memory address having regard to the constraining information of the associated capability; and to enable performance of the memory access operation for each data element for which the memory access operation is allowed.
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公开(公告)号：US11907301B2
公开(公告)日：2024-02-20
申请号：US17260109
申请日：2019-06-06
Applicant: Arm Limited
IPC: G06F16/903 , G06F12/1009 , G06F12/14
CPC classification number: G06F16/90339 , G06F12/1009 , G06F12/1483 , G06F16/90348
Abstract: A control table (22) defines information for controlling a processing component (20) to perform an operation. The table (22) comprises entries each corresponding to a variable size region defined by a first limit address and one of a second limit address and size. A binary search procedure is provided for looking up the table, comprising a number of search window narrowing steps, each narrowing a current search window of candidate entries to a narrower search window comprising fewer entries, based on a comparison of a query address against the first limit address of a selected candidate entry of the current search window. The comparison is independent of the second limit address or size of the selected candidate entry. After the search window is narrowed to a single entry, the query address is compared with the second limit address or size of that single entry.
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公开(公告)号：US11714641B2
公开(公告)日：2023-08-01
申请号：US16471185
申请日：2017-11-08
Applicant: ARM LIMITED
CPC classification number: G06F9/30036 , G06F9/3013 , G06F9/30043 , G06F9/30112 , G06F9/345 , G06F9/3552 , G06F9/3555
Abstract: An apparatus and method are provided for performing vector processing operations. In particular the apparatus has processing circuitry to perform the vector processing operations and an instruction decoder to decode vector instructions to control the processing circuitry to perform the vector processing operations specified by the vector instructions. The instruction decoder is responsive to a vector generating instruction identifying a scalar start value and wrapping control information, to control the processing circuitry to generate a vector comprising a plurality of elements. In particular, the processing circuitry is arranged to generate the vector such that the first element in the plurality is dependent on the scalar start value, and the values of the plurality of elements follow a regularly progressing sequence that is constrained to wrap as required to ensure that each value is within bounds determined from the wrapping control information. The vector generating instruction can be useful in a variety of situations, a particular use case being to implement a circular addressing mode within memory, where the vector generating instruction can be coupled with an associated vector memory access instruction. Such an approach can remove the need to provide additional logic within the memory access path to support such circular addressing.
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公开(公告)号：US11663007B2
公开(公告)日：2023-05-30
申请号：US17492068
申请日：2021-10-01
Applicant: Arm Limited
CPC classification number: G06F9/30065 , G06F9/325 , G06F9/3846
Abstract: In response to decoding a zero-overhead loop control instruction of an instruction set architecture, processing circuitry sets at least one loop control parameter for controlling execution of one or more iterations of a program loop body of a zero-overhead loop. Based on the at least one loop control parameter, loop control circuitry controls execution of the one or more iterations of the program loop body of the zero-overhead loop, the program loop body excluding the zero-overhead loop control instruction. Branch prediction disabling circuitry detects whether the processing circuitry is executing the program loop body of the zero-overhead loop associated with the zero-overhead loop control instruction, and dependent on detecting that the processing circuitry is executing the program loop body of the zero-overhead loop, disables branch prediction circuitry. This reduces power consumption during a zero-overhead loop when the branch prediction circuitry is unlikely to provide a benefit.
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