-
公开(公告)号：US09430381B2
公开(公告)日：2016-08-30
申请号：US14257090
申请日：2014-04-21
Applicant: ARM Limited
Inventor： Andreas Due Engh-Halstvedt , Jorn Nystad
CPC classification number: G06F12/0802 , G06T1/20 , G09G5/39
Abstract: A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the texture pipeline in a variable order corresponding to the order in which they are retrieved from a memory 4. If the texture values are floating point texture values, then they are processed in a fixed order in order to ensure result invariants as the filter operation is non-associative for floating point values. The filter operation is not commenced until all of the floating point texture values have been retrieved from the memory 4 and other available for processing.
Abstract translation: 图形处理单元2包括对纹理值执行滤波操作的纹理管线6。 如果纹理值是整数纹理值，则它们可以由纹理流水线以与从存储器4检索的顺序相对应的可变顺序来处理。如果纹理值是浮点纹理值，则它们被处理 以固定顺序，以确保结果不变量，因为过滤器操作对于浮点值是非关联的。 过滤器操作不会开始，直到从存储器4检索到所有浮点纹理值，并且可以处理的其他值。
-
公开(公告)号：US20150228050A1
公开(公告)日：2015-08-13
申请号：US14691572
申请日：2015-04-20
Applicant: ARM LIMITED
Inventor： Jorn Nystad , Anders Lassen
CPC classification number: G06T1/20 , G06T9/00 , G06T9/005 , G06T11/001 , H04N19/90
Abstract: When encoding a texture map 1 for use in graphics processing, the texture map is divided into a plurality of equal-sized blocks 2 of texture data elements. Each block 2 of texture data elements is then encoded as a block of texture data 5 that includes a set of integer values to be used to generate a set of base data values for the block, and a set of index values indicating how to use the base data values to generate data values for the texture data elements that the block represents. The integer values and the index values are both encoded in an encoded texture data block using a combination of base-n values, where n is greater than two, and base-2 values. Predefined bit representations are used to represent plural base-n values (n>2) collectively, and the bits of the bit representations representing the base-n values (n>2) are interleaved with bits representing the base-2 values in the encoded texture data block.
Abstract translation: 当对用于图形处理的纹理图1进行编码时，纹理映射被分成纹理数据元素的多个等大小的块2。 纹理数据元素的每个块2然后被编码为纹理数据块5，该纹理数据块5包括用于生成该块的基本数据值集合的一组整数值，以及一组指示如何使用 基本数据值以生成块表示的纹理数据元素的数据值。 整数值和索引值都使用base-n值（其中n大于2）和base-2值的组合编码在编码纹理数据块中。 预定义位表示用于统一表示多个基n值（n> 2），表示基n值（n> 2）的比特表示的比特与编码的基本n值 纹理数据块。
-
公开(公告)号：US20150062154A1
公开(公告)日：2015-03-05
申请号：US14015897
申请日：2013-08-30
Applicant: ARM Limited
Inventor： Sean Tristram Ellis , Jorn Nystad , Andreas Engh-Halstvedt
IPC: G06T1/20
CPC classification number: G06T15/005 , G06T11/40
Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).
Abstract translation: 当处理一组瓦片以在基于瓦片的图形处理流水线中生成输出时，对于该瓦片组的一个或多个瓦片，流水线呈现包含要在处理操作（602）中使用的数据的一个或多个渲染目标， 并将渲染目标存储在瓦片缓冲器（604）中。 当处理一组瓦片（606）的相邻瓦片时，它还存储一些而不是所有的渲染目标的采样位置值或用于使用的目标。 然后，它使用存储的渲染目标或目标（608）和来自瓦片组（610）的另一个相邻瓦片的一个或多个存储的采样位置值来执行瓦片的处理操作，以生成瓦片（612）的输出 ）。
-
公开(公告)号：US20150046655A1
公开(公告)日：2015-02-12
申请号：US13962905
申请日：2013-08-08
Applicant: ARM Limited
Inventor： Jorn Nystad , Andreas Engh-Halstvedt
IPC: G06F12/08
CPC classification number: G06F12/0875 , G06F9/3004 , G06F9/3824 , G06F9/3828 , G06F9/3834 , G06F9/3851 , G06F9/3887 , G06F12/0815 , G06F12/0842 , G06T1/60
Abstract: A data processing system includes one or more processors 4, 5, 6, 7 operable to initiate atomic memory requests for execution threads and plural data caches 8, 9, 10, 11 that are used to store data needed to perform an atomic memory operation when an atomic memory operation is to be performed.When atomic operations are to be performed against a data cache, the results of atomic operations that are to access the same memory location are accumulated in a temporary cache line in the data cache pending the arrival in the cache of the “true” cache line from memory. The accumulated results of the atomic operations stored in the temporary cache line are then combined with the cache line from memory when the cache line arrives in the cache. Individual atomic values can also be reconstructed once the cache line arrives at the cache.
Abstract translation: 数据处理系统包括一个或多个处理器4,5,6,7，其可操作以发起用于执行线程的原子存储器请求以及用于存储执行原子存储器操作所需的数据的多个数据高速缓存8,9,10,11，当 将执行原子存储器操作。 当要针对数据高速缓存执行原子操作时，访问同一内存位置的原子操作的结果将累积在数据高速缓存中的临时高速缓存行中，等待到达“真”高速缓存行的高速缓存中 记忆。 然后，当高速缓存行到达缓存时，存储在临时高速缓存行中的原子操作的累积结果与来自存储器的高速缓存行组合。 一旦高速缓存行到达高速缓存，也可以重构单个原子值。
-
公开(公告)号：US20140366033A1
公开(公告)日：2014-12-11
申请号：US13913334
申请日：2013-06-07
Applicant: ARM Limited
Inventor： Jorn Nystad
IPC: G06F9/50
CPC classification number: G06F9/50 , G06F9/3001 , G06F9/3004 , G06F9/30076 , G06F9/3834 , G06F9/3851 , G06F9/3887 , G06F9/5016 , G06F9/52 , G06F12/0284 , G06F2209/5018 , G06F2209/521
Abstract: When an atomic operation is to be executed for a thread group by an execution stage of a data processing system, it is determined whether there is a set of threads for which the atomic operation for the threads accesses the same memory location. If so, the arithmetic operation for the atomic operation is performed for the first thread in the set of threads using an identity value for the arithmetic operation for the atomic operation and the first thread's register value for the atomic operation, and is performed for each other thread in the set of threads using the thread's register value for the atomic operation and the result of the arithmetic operation for the preceding thread in the set of threads, to thereby generate for the final thread in the identified set of threads a combined result of the arithmetic operation for the set of threads.
Abstract translation: 当通过数据处理系统的执行阶段对线程组执行原子操作时，确定是否存在用于线程的原子操作访问相同存储器位置的一组线程。 如果是这样，使用原子操作的算术运算的标识值和原子操作的第一线程的寄存器值，对线程组中的第一线程执行原子操作的算术运算，并且彼此执行 在线程组中的线程使用线程的寄存器值进行原子操作，并对该线程中前一个线程的算术运算结果进行生成，从而为所识别的线程组中的最终线程生成一个组合结果 算术运算的一组线程。
-
Patent Agency Ranking
公开(公告)号：US11189005B1
公开(公告)日：2021-11-30
申请号：US17004797
申请日：2020-08-27
Applicant: Arm Limited
Abstract: A method of operating a graphics processor that is configured to execute a graphics processing pipeline is provided. The method comprises the graphics processor reading, from an index buffer in external memory, a block of data comprising plural sets of indices, each set of indices comprising a sequence of indices indexing a set of vertices that defines a primitive of a plurality of primitives to be processed by the graphics processing pipeline. The graphics processor compresses the block of data to form a compressed version of the block of data, and stores the compressed version of the block of data in an internal memory of the graphics processor.
-
公开(公告)号：US10607400B2
公开(公告)日：2020-03-31
申请号：US15594969
申请日：2017-05-15
Applicant: ARM Limited
Inventor： Sandeep Kakarlapudi , Jorn Nystad , Andreas Due-Engh Halstvedt
Abstract: A graphics processing pipeline comprises vertex shading circuitry that operates to vertex shade position attributes of vertices of a set of vertices to be processed by the graphics processing pipeline, to generate, inter alia, a separate vertex shaded position attribute value for each view of the plural different views. Tiling circuitry then determines for the vertices that have been subjected to the first vertex shading operation, whether the vertices should be processed further. Vertex shading circuitry then performs a second vertex shading operation on the vertices that it has been determined should be processed further, to vertex shade the remaining vertex attributes for each vertex that it has been determined should be processed further, to generate, inter alia, a single vertex shaded attribute value for the set of plural views.
-
公开(公告)号：US10593093B2
公开(公告)日：2020-03-17
申请号：US15747636
申请日：2016-07-22
Applicant: Arm Limited
Inventor： Jorn Nystad
Abstract: A programmable execution unit (42) of a graphics processor includes a functional unit (50) that is operable to execute instructions (51). The output of the functional unit (50) can both be written to a register file (46) and fed back directly as an input to the functional unit by means of a feedback circuit (52). Correspondingly, an instruction that is to be executed by the functional unit (50) can select as its inputs either the fed-back output (52) from the execution of the previous instruction, or inputs from the registers (46). A register access descriptor (54) between each instruction in a group of instructions (53) specifies the registers whose values will be available on the register ports that the functional unit will read when executing the instruction, and the register address where the result of the execution of the instruction will be written to. The programmable execution unit (42) executes group of instructions (53) that are to be executed atomically.
-
公开(公告)号：US10176546B2
公开(公告)日：2019-01-08
申请号：US13933612
申请日：2013-07-02
Applicant: ARM Limited
Inventor： Jorn Nystad
Abstract: A data processing system determines for a stream of instructions to be executed, whether there are any instructions that can be re-ordered in the instruction stream 41 and assigns each such instruction to an instruction completion tracker and includes in the encoding for the instruction an indication of the instruction completion tracker it has been assigned to 42. For each instruction in the instruction stream, an indication of which instruction completion trackers, if any, the instruction depends on is also provided 43, 44. Then, when an instruction that is indicated as being dependent on an instruction completion tracker is to be executed, the status of the relevant instruction completion tracker is checked before executing the instruction.
-
公开(公告)号：US10157132B1
公开(公告)日：2018-12-18
申请号：US15661200
申请日：2017-07-27
Applicant: ARM Limited
Inventor： Edvard Fielding , Andreas Due Engh-Halstvedt , Jorn Nystad , Antonio Garcia Guirado , William Robert Stoye , Ian Rudolf Bratt
IPC: G06F12/00 , G06F13/00 , G06F13/28 , G06F12/0811 , G06F12/0875 , G06F12/0862 , G06F12/0846 , G06F12/0868
Abstract: A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.
-
-
-
-
-
-
-
-
-
Search Results
84
records
(took 0.02 seconds)
