公开(公告)号：US20210028788A1

公开(公告)日：2021-01-28

申请号：US16522461

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Saurabh Pijuskumar Sinha ,  Sheng-En Hung ,  Chien-Ju Chao

IPC: H03L7/08 ,  G06F1/06 ,  G06F1/10 ,  G06F1/12

Abstract: Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

公开(公告)号：US10599806B2

公开(公告)日：2020-03-24

申请号：US15939047

申请日：2018-03-28

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without the inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without the inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without the inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

公开(公告)号：US20220382690A1

公开(公告)日：2022-12-01

申请号：US17334960

申请日：2021-05-31

Applicant: Arm Limited

Inventor： Paul Nicholas Whatmough ,  Zhi-Gang Liu ,  Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Matthew Mattina

IPC: G06F13/16 ,  G06F13/40

Abstract: Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.

公开(公告)号：US20210390059A1

公开(公告)日：2021-12-16

申请号：US16901720

申请日：2020-06-15

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Douglas Joseph ,  Saurabh Pijuskumar Sinha

IPC: G06F12/0897 ,  G06F12/0895 ,  G06F12/0811 ,  G06F12/06

Abstract: Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.

公开(公告)号：US20210389520A1

公开(公告)日：2021-12-16

申请号：US17288498

申请日：2019-10-23

Applicant: Arm Limited

Inventor： Vinay Vashishtha ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Gregory Munson Yeric

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42

Abstract: Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

公开(公告)号：US11120191B2

公开(公告)日：2021-09-14

申请号：US16820471

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/522 ,  G06F111/04 ,  G06F111/20

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized locations or legal locations.

公开(公告)号：US11081469B2

公开(公告)日：2021-08-03

申请号：US16580349

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar Sinha ,  Joel Thornton Irby ,  Supreet Jeloka

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/66 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.

公开(公告)号：US10657218B2

公开(公告)日：2020-05-19

申请号：US15826649

申请日：2017-11-29

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Stephen Lewis Moore

IPC: G06F17/50

Abstract: Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

公开(公告)号：US11966785B2

公开(公告)日：2024-04-23

申请号：US16943117

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Dam Sunwoo ,  Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Jaekyu Lee ,  Jose Alberto Joao ,  Krishnendra Nathella

IPC: G06F9/46 ,  G06F9/50 ,  G06N5/04 ,  G06N20/00

CPC classification number: G06F9/5044 ,  G06F9/5038 ,  G06F9/505 ,  G06N5/04 ,  G06N20/00

Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.

公开(公告)号：US20230354571A1

公开(公告)日：2023-11-02

申请号：US18012917

申请日：2021-06-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Yew Keong Chong

IPC: H10B10/00

CPC classification number: H10B10/12

Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.