公开(公告)号：US11119961B2

公开(公告)日：2021-09-14

申请号：US16655403

申请日：2019-10-17

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Dimitrios Kaseridis

IPC: G06F13/00 ,  G06F13/40 ,  G06F12/0811 ,  G06F12/0817 ,  G06F13/16

Abstract: A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.

公开(公告)号：US09900260B2

公开(公告)日：2018-02-20

申请号：US14965237

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Ramamoorthy Guru Prasadh ,  Jamshed Jalal ,  Ashok Kumar Tummala ,  Phanindra Kumar Mannava ,  Tushar P. Ringe

IPC: H04L12/891 ,  H04L12/26 ,  H04L12/835 ,  H04L29/06

CPC classification number: H04L47/41 ,  H04L43/106 ,  H04L43/16 ,  H04L47/30 ,  H04L69/08 ,  H04L69/18 ,  H04L69/22

Abstract: A bridging circuit and method of operation thereof, which couples first and second electronic circuits of a data processing system. The first electronic circuit generates signals corresponding to digits of a flow control unit (flit) of a first flow control protocol and where the second electronic circuit is responsive to signals corresponding to flits of a second flow control protocol. When first flits are destined for the same target buffer, they are combined to provide a second flit consistent with the second flow control protocol and transmitting the second flit to the second electronic circuit. The second flit includes data and metadata fields copied from the first flits, a common field common to each of the first flits, a merged field containing a merger of fields from the first flits and a validity field indicating which portions of the second flit contain valid data.

公开(公告)号：US11899607B2

公开(公告)日：2024-02-13

申请号：US17335378

申请日：2021-06-01

Applicant: Arm Limited

Inventor： Timothy Hayes ,  Alejandro Rico Carro ,  Tushar P. Ringe ,  Kishore Kumar Jagadeesha

IPC: G06F13/40 ,  G06F12/0875

CPC classification number: G06F13/4031 ,  G06F12/0875 ,  G06F2212/1024

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

公开(公告)号：US20220164288A1

公开(公告)日：2022-05-26

申请号：US17102997

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P. Ringe ,  Mukesh Patel ,  Sakshi Verma

IPC: G06F12/0815

Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.

公开(公告)号：US20210058335A1

公开(公告)日：2021-02-25

申请号：US16550018

申请日：2019-08-23

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Kishore Kumar Jagadeesha

IPC: H04L12/863 ,  H04L12/801 ,  H04L12/46 ,  H04L12/835

Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.

公开(公告)号：US10917198B2

公开(公告)日：2021-02-09

申请号：US16027864

申请日：2018-07-05

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Tushar P. Ringe

IPC: H04L29/08 ,  H04L1/16

Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

公开(公告)号：US10802534B2

公开(公告)日：2020-10-13

申请号：US16256675

申请日：2019-01-24

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/10 ,  G06F1/08 ,  H03L7/091 ,  H03L7/081 ,  G06F1/24

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

公开(公告)号：US20200301854A1

公开(公告)日：2020-09-24

申请号：US16361728

申请日：2019-03-22

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Tushar P. Ringe ,  Mukesh Patel ,  Jamshed Jalal ,  Ashok Kumar Tummala ,  Mark David Werkheiser

IPC: G06F12/14 ,  G06F12/0817 ,  G06F9/54

Abstract: A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.

公开(公告)号：US10585449B1

公开(公告)日：2020-03-10

申请号：US16248456

申请日：2019-01-15

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/099

Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.