公开(公告)号：US09665514B2

公开(公告)日：2017-05-30

申请号：US14045172

申请日：2013-10-03

Applicant: ARM LIMITED

Inventor： Ramamoorthy Guru Prasadh

IPC: G06F13/37 ,  G06F13/38

CPC classification number: G06F13/37 ,  G06F13/385

Abstract: A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state.

公开(公告)号：US09900260B2

公开(公告)日：2018-02-20

申请号：US14965237

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Ramamoorthy Guru Prasadh ,  Jamshed Jalal ,  Ashok Kumar Tummala ,  Phanindra Kumar Mannava ,  Tushar P. Ringe

IPC: H04L12/891 ,  H04L12/26 ,  H04L12/835 ,  H04L29/06

CPC classification number: H04L47/41 ,  H04L43/106 ,  H04L43/16 ,  H04L47/30 ,  H04L69/08 ,  H04L69/18 ,  H04L69/22

Abstract: A bridging circuit and method of operation thereof, which couples first and second electronic circuits of a data processing system. The first electronic circuit generates signals corresponding to digits of a flow control unit (flit) of a first flow control protocol and where the second electronic circuit is responsive to signals corresponding to flits of a second flow control protocol. When first flits are destined for the same target buffer, they are combined to provide a second flit consistent with the second flow control protocol and transmitting the second flit to the second electronic circuit. The second flit includes data and metadata fields copied from the first flits, a common field common to each of the first flits, a merged field containing a merger of fields from the first flits and a validity field indicating which portions of the second flit contain valid data.

公开(公告)号：US11181957B1

公开(公告)日：2021-11-23

申请号：US17102963

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Ramamoorthy Guru Prasadh ,  Tushar P Ringe ,  Kishore Kumar Jagadeesha ,  David Joseph Hawkins ,  Saira Samar Malik

IPC: G06F1/24 ,  H03K19/20 ,  G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K5/00

Abstract: An improved apparatus and method for the protection of reset in systems with stringent safety goals that employ primary and shadow logic blocks with a lock-step checker to achieve functional safety, including those systems having very large fanout of primary and shadow reset signal trees. The disclosed apparatus and method support assertion of reset that is asynchronous to the system clock and deassertion of reset that is synchronous to the system clock. Shadow logic blocks have reset deasserted a fixed number of clock cycles after their respective primary logic blocks, thereby avoiding the requirement to synchronize the primary and shadow reset signal trees at each of their end points to ensure lock-step operation between the primary and shadow logic blocks.

公开(公告)号：US20200241589A1

公开(公告)日：2020-07-30

申请号：US16256675

申请日：2019-01-24

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/10 ,  G06F1/08

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

公开(公告)号：US10802534B2

公开(公告)日：2020-10-13

申请号：US16256675

申请日：2019-01-24

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/10 ,  G06F1/08 ,  H03L7/091 ,  H03L7/081 ,  G06F1/24

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

公开(公告)号：US10585449B1

公开(公告)日：2020-03-10

申请号：US16248456

申请日：2019-01-15

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/099

Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.