公开(公告)号：US20210056889A1

公开(公告)日：2021-02-25

申请号：US16828928

申请日：2020-03-24

Applicant: Au Optronics Corporation

Inventor： Hsien-Chun Wang ,  Ya-Jung Wang ,  Jing-Wun Jhang ,  Chen-Feng Fan ,  Wan-Heng Chang ,  Sung-Yu Su

IPC: G09G3/32

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

公开(公告)号：US10854166B2

公开(公告)日：2020-12-01

申请号：US16723346

申请日：2019-12-20

Applicant: AU Optronics Corporation

Inventor： Peng-Bo Xi ,  Sung-Yu Su

IPC: G09G5/00 ,  H03K17/693 ,  G09G3/00 ,  G09G3/20 ,  G09G3/36 ,  H03K17/00

Abstract: A multiplexer is provided herein. The multiplexer has a plurality of first driving units and a plurality of second driving units. Each of the first driving units has a first data voltage input terminal, and each of the second driving units has a second data voltage input terminal. The first data voltage input terminal and the second data voltage input terminal are configured to receive pixel voltage signals with different polarities. In the first driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a first reset signal, wherein the transistor of the first driving unit is coupled to the first data voltage input terminal and a first data line. In the second driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a second reset signal, wherein the transistor of the second driving unit is coupled to the second data voltage input terminal and a second data line.

公开(公告)号：US20200350337A1

公开(公告)日：2020-11-05

申请号：US16589163

申请日：2019-10-01

Applicant: Au Optronics Corporation

Inventor： Yu-Min Chi ,  Sung-Yu Su ,  Chen-Feng Fan

IPC: H01L27/12 ,  G06F3/044

Abstract: A pixel array substrate includes a substrate, a first patterned conductive layer, a pixel electrode layer, a semiconductor pattern layer, a first dielectric layer, a second patterned conductive layer, a second dielectric layer, and a common electrode layer. The first patterned conductive layer includes first and second scan lines, first and second gates, and first and second connection electrodes. The pixel electrode layer includes first and second pixel electrodes. The semiconductor pattern layer includes first and second patterns. The second patterned conductive layer includes first and second data lines, first and second sources, first and second drains, and a touch wire. The common electrode layer includes a common electrode and first and second transferring electrodes. The first transferring electrode is electrically connected to the first connection electrode and the first drain. The second transferring electrode is electrically connected to the second connection electrode and the second drain.

公开(公告)号：US20200073499A1

公开(公告)日：2020-03-05

申请号：US16435585

申请日：2019-06-10

Applicant: Au Optronics Corporation

Inventor： Yu-Min Chi ,  Sung-Yu Su

IPC: G06F3/041 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362

Abstract: A touch panel includes a substrate, scan lines, data lines, sub-pixels, a first conductive line, a second conductive line, and a conductive layer. The sub-pixels are arranged in columns along a first direction and arranged in rows along a second direction. Each of the sub-pixels includes an active element and a pixel electrode electrically connected with the active element. The active element is electrically connected with a corresponding scan line and a corresponding data line. The conductive layer overlaps the sub-pixels. The conductive layer includes a first electrode and a second electrode. The first electrode is electrically connected with the first conductive line. The second electrode is electrically connected with the second conductive line. The second electrode is separated from the first electrode. One of the first electrode and the second electrode is a touch electrode, and another one is a common electrode.

公开(公告)号：US10379406B2

公开(公告)日：2019-08-13

申请号：US15697570

申请日：2017-09-07

Applicant: AU Optronics Corporation

Inventor： Yu-Min Chi ,  Sung-Yu Su

IPC: G02F1/1343 ,  G09G3/36 ,  G02F1/1337

Abstract: A display panel includes a pair of substrates, a pixel electrode, a common electrode, a first transparent electrode, and a second transparent electrode. A plurality of sub pixels is defined on the pair of substrates. The first transparent electrode corresponds to at least one of the plurality of sub pixels. A vertical projection of the first transparent electrode, a vertical projection of a part of the pixel electrode of the sub pixel corresponding to the first transparent electrode, and a vertical projection of a part of the common electrode of the sub pixel corresponding to the first transparent electrode on the substrates are overlapped. The second transparent electrode corresponds to the corresponding sub pixel. A vertical projection of the second transparent electrode, a vertical projection of another part of the pixel electrode of the sub pixel corresponding to the second transparent electrode, and a vertical projection of another part of the common electrode of the sub pixel corresponding to the second transparent electrode on the substrates are overlapped. A gap exists between the first transparent electrode and the second transparent electrode.

公开(公告)号：US10379403B2

公开(公告)日：2019-08-13

申请号：US15802017

申请日：2017-11-02

Applicant: AU OPTRONICS CORPORATION

Inventor： Peng-Bo Xi ,  Sung-Yu Su ,  Chu-Hsuan I

IPC: G02F1/1337 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12

Abstract: A method for manufacturing a pixel unit includes the following steps. A channel layer is formed. A first pattern layer is formed above the channel layer and includes a scan line and a gate electrode. A second pattern layer is formed above the first pattern layer and includes a data line and a source electrode, where the source electrode is electrically connected to the channel layer. A third pattern layer is formed above the second pattern layer and includes a drain electrode and an auxiliary electrode, where the drain electrode is electrically connected to the channel layer. The auxiliary electrode is electrically connected to the scan line through a first contact hole.

公开(公告)号：US10303012B2

公开(公告)日：2019-05-28

申请号：US15918052

申请日：2018-03-12

Applicant: AU Optronics Corporation

Inventor： Kung-Ching Chu ,  Yu-min Chi ,  Chen-Feng Fan ,  Sung-Yu Su

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  H01L27/12

Abstract: A pixel structure includes first and second gate lines, at least one data line, and a pixel unit. The pixel unit has first and second display areas and includes first and second active devices, a first pixel electrode layer, a common electrode layer, and a second pixel electrode layer. The first and second active devices are electrically connected to the first and second gate lines, respectively. The first pixel electrode layer is electrically connected to the first active device. The common electrode layer is disposed above the first pixel electrode layer and includes first and second portions which are located at the first and second display areas, respectively. The second pixel electrode layer is electrically connected to the second active device, and is located above the first portion of the common electrode layer but not above the second portion, where the second pixel electrode layer has a first slit pattern and the second portion of the common electrode layer has a second slit pattern.

公开(公告)号：US10216017B2

公开(公告)日：2019-02-26

申请号：US15393954

申请日：2016-12-29

Applicant: AU OPTRONICS CORPORATION

Inventor： Wan-Heng Chang ,  Chen-Feng Fan ,  Rong-Fu Lin ,  Sung-Yu Su ,  Hsiao-Wei Cheng

IPC: G02F1/13 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1337 ,  G02F1/1343 ,  G02F1/1347

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, a third substrate, a pixel electrode layer, a first common electrode layer, a first control electrode layer, a first liquid crystal layer, a second common electrode layer, a second control electrode layer and a second liquid crystal layer. The second substrate is opposite to the first substrate. The third substrate is opposite to the second substrate. The pixel electrode layer and the first common electrode layer are disposed on the first substrate. The first control electrode layer is disposed on the second substrate. The first liquid crystal layer is disposed between the first substrate and the second substrate. The second common electrode layer is disposed on the second substrate. The second control electrode layer is disposed on the third substrate. The second liquid crystal layer is disposed between the second substrate and the third substrate.

公开(公告)号：US20160054625A1

公开(公告)日：2016-02-25

申请号：US14530838

申请日：2014-11-03

Applicant: Au Optronics Corporation

Inventor： Tai-Li Hsia ,  Ya-Jung Wang ,  Sung-Yu Su

IPC: G02F1/1343 ,  G02F1/1333 ,  G02F1/1368

CPC classification number: G02F1/134309 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2201/121 ,  H01L27/124

Abstract: A liquid crystal display panel including an array substrate, an opposite substrate disposed opposite to the array substrate and liquid crystal medium between the opposite substrate and the array substrate is provided. The array substrate includes a passivation layer, an insulation layer and a first electrode. The passivation layer has a contact hole. The insulation layer is disposed on the passivation layer and has a concave at a portion overlapped with the contact hole. The first electrode is disposed on the passivation layer and the insulation layer, and has a main portion and stripe portions, wherein a gap is formed between the two adjacent stripe portions. Each stripe portion has a connection portion, at least one turning point and an extending portion. Each connection portion is directly connected to the main portion, and the contact hole is overlapped with at least one connection portion.

Abstract translation: 提供一种液晶显示面板，包括阵列基板，与阵列基板相对设置的相对基板和在相对基板和阵列基板之间的液晶介质。 阵列基板包括钝化层，绝缘层和第一电极。 钝化层具有接触孔。 绝缘层设置在钝化层上，并且在与接触孔重叠的部分处具有凹陷。 第一电极设置在钝化层和绝缘层上，并且具有主要部分和条纹部分，其中在两个相邻条纹部分之间形成间隙。 每个条纹部分具有连接部分，至少一个转折点和延伸部分。 每个连接部分直接连接到主要部分，并且接触孔与至少一个连接部分重叠。

公开(公告)号：US11887529B2

公开(公告)日：2024-01-30

申请号：US17723472

申请日：2022-04-19

Applicant: Au Optronics Corporation

Inventor： Ya-Jung Wang ,  Jing-Wun Jhang ,  Rong-Fu Lin ,  Nien-Chen Li ,  Hsien-Chun Wang ,  Che-Chia Chang ,  June Woo Lee ,  Hsin-Ying Lin ,  Chia-Ting Hsieh ,  Chien-Fu Huang ,  Sung-Yu Su

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2330/021

Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.