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    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT
    12.
    发明申请
    OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190326272A1

    公开(公告)日：2019-10-24

    申请号：US15958169

    申请日：2018-04-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

    Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

    SEMICONDUCTOR CHIP DEVICE
    14.
    发明公开
    SEMICONDUCTOR CHIP DEVICE 审中-公开

    公开(公告)号：US20230187364A1

    公开(公告)日：2023-06-15

    申请号：US17644191

    申请日：2021-12-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Chia-Hao Cheng ,  Kong Toon Ng ,  Rahul Agarwal ,  Brett P. Wilkerson

    IPC: H01L23/538 ,  H01L21/48

    CPC classification number: H01L23/5384 ,  H01L21/486

    Abstract: An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.

    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS
    16.
    发明申请
    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS 有权

    公开(公告)号：US20210098441A1

    公开(公告)日：2021-04-01

    申请号：US16586309

    申请日：2019-09-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John J. Wuu ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Rahul Agarwal

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

    FAN-OUT PACKAGE WITH REINFORCING RIVETS
    17.
    发明申请
    FAN-OUT PACKAGE WITH REINFORCING RIVETS 有权

    公开(公告)号：US20210057352A1

    公开(公告)日：2021-02-25

    申请号：US16544021

    申请日：2019-08-19

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah ,  Chia-Hao Cheng ,  Brett P. Wilkerson ,  Lei Fu

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

    MOLDED CHIP PACKAGE WITH ANCHOR STRUCTURES
    18.
    发明申请
    MOLDED CHIP PACKAGE WITH ANCHOR STRUCTURES 有权

    公开(公告)号：US20210020459A1

    公开(公告)日：2021-01-21

    申请号：US16513450

    申请日：2019-07-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Lei Fu ,  Rahul Agarwal

    IPC: H01L21/56 ,  H01L23/31

    Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

    Offset-aligned three-dimensional integrated circuit
    19.
    发明授权
    Offset-aligned three-dimensional integrated circuit 有权

    公开(公告)号：US10573630B2

    公开(公告)日：2020-02-25

    申请号：US15958169

    申请日：2018-04-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

    IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

    Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

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