公开(公告)号：US20220392882A1

公开(公告)日：2022-12-08

申请号：US17891444

申请日：2022-08-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

公开(公告)号：US11309222B2

公开(公告)日：2022-04-19

申请号：US16556105

申请日：2019-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lei Fu ,  Milind S. Bhagavat ,  Chia-Hao Cheng

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/00

Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.

公开(公告)号：US11018125B2

公开(公告)日：2021-05-25

申请号：US16927111

申请日：2020-07-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/433

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US20200294923A1

公开(公告)日：2020-09-17

申请号：US16887184

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Lei Fu ,  Farshad Ghahghahi

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

Abstract: Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.

公开(公告)号：US20200185367A1

公开(公告)日：2020-06-11

申请号：US16215969

申请日：2018-12-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56

Abstract: In at least one embodiment, an integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, and a discrete device disposed laterally with respect to the integrated circuit die and disposed above the redistribution layer. The integrated circuit product may include encapsulant mechanically coupling the redistribution layer, the integrated circuit die, and the discrete device. The integrated circuit product may include first conductive vias through the redistribution layer and second conductive vias through the redistribution layer. The first conductive vias may be electrically coupled to the integrated circuit die and the second conductive vias being electrically coupled to the discrete device. The discrete device may include a discrete capacitor device made from a ceramic material, electrolytic materials, or electrochemical materials.

公开(公告)号：US20200168549A1

公开(公告)日：2020-05-28

申请号：US16778815

申请日：2020-01-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US20190393124A1

公开(公告)日：2019-12-26

申请号：US16563138

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US12183675B2

公开(公告)日：2024-12-31

申请号：US16351728

申请日：2019-03-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Chia-Hao Cheng ,  Milind S. Bhagavat

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

公开(公告)号：US11670624B2

公开(公告)日：2023-06-06

申请号：US17120753

申请日：2020-12-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49827 ,  H01L28/40

Abstract: An integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, a row of discrete devices disposed laterally with respect to the integrated circuit die, and encapsulant mechanically coupling the redistribution layer, integrated circuit die, and the row of discrete devices. In at least one embodiment, the row of discrete devices is a row of decoupling capacitors disposed proximate to the integrated circuit die and coupled to the integrated circuit die and a power distribution network. In at least one embodiment, a second integrated circuit die is disposed above the redistribution layer and disposed laterally with respect to the integrated circuit die and the row of discrete devices. The second integrated circuit die is mechanically coupled to the redistribution layer, integrated circuit die, and the row of discrete devices and is partially surrounded by the row of discrete devices.

公开(公告)号：US11658123B2

公开(公告)日：2023-05-23

申请号：US17032544

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L24/13 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/13024 ,  H01L2224/24137 ,  H01L2224/24991 ,  H01L2224/25171 ,  H01L2224/25174 ,  H01L2224/25177 ,  H01L2224/82801

Abstract: A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).