公开(公告)号：US20200066677A1

公开(公告)日：2020-02-27

申请号：US16110678

申请日：2018-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind Bhagavat ,  David Hugh McIntyre ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.

公开(公告)号：US10923430B2

公开(公告)日：2021-02-16

申请号：US16458094

申请日：2019-06-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Chun-Hung Lin ,  Rahul Agarwal ,  Milind Bhagavat ,  Fei Guo

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer and an interconnect chip at least partially encased in the first molding layer. The interconnect chip has a first side and a second side opposite the first side and a polymer layer on the first side. The polymer layer includes plural conductor traces. A redistribution layer (RDL) structure is positioned on the first molding layer and has plural conductor structures electrically connected to the plural conductor traces. The plural conductor traces provide lateral routing.

公开(公告)号：US20190326272A1

公开(公告)日：2019-10-24

申请号：US15958169

申请日：2018-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

公开(公告)号：US20240063206A1

公开(公告)日：2024-02-22

申请号：US18497961

申请日：2023-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Milind Bhagavat ,  Brett Wilkerson ,  Rahul Agarwal

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/08146

Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

公开(公告)号：US11495588B2

公开(公告)日：2022-11-08

申请号：US16213347

申请日：2018-12-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Milind Bhagavat ,  Rahul Agarwal

IPC: H01L25/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34 ,  H05K3/28

Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.

公开(公告)号：US11011495B2

公开(公告)日：2021-05-18

申请号：US16110678

申请日：2018-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind Bhagavat ,  David Hugh McIntyre ,  Rahul Agarwal

IPC: H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H02M3/158 ,  H02M3/07

Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.

公开(公告)号：US10573630B2

公开(公告)日：2020-02-25

申请号：US15958169

申请日：2018-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.