公开(公告)号：US11656945B2

公开(公告)日：2023-05-23

申请号：US17133843

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Nuwan Jayasena ,  Sudhanva Gurumurthi ,  Shaizeen Aga ,  Shrikanth Ganapathy

IPC: G06F11/14 ,  G06F9/38

CPC classification number: G06F11/141 ,  G06F9/3877

Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.

公开(公告)号：US11409608B2

公开(公告)日：2022-08-09

申请号：US17136549

申请日：2020-12-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Shrikanth Ganapathy ,  Ross V. La Fetra ,  John Kalamatianos ,  Sudhanva Gurumurthi ,  Shaizeen Aga ,  Vilas Sridharan ,  Michael Ignatowski ,  Nuwan Jayasena

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/10

Abstract: Providing host-based error detection capabilities in a remote execution device is disclosed. A remote execution device performs a host-offloaded operation that modifies a block of data stored in memory. Metadata is generated locally for the modified of block of data such that the local metadata generation emulates host-based metadata generation. Stored metadata for the block of data is updated with the locally generated metadata for the modified portion of the block of data. When the host performs an integrity check on the modified block of data using the updated metadata, the host does not distinguish between metadata generated by the host and metadata generated in the remote execution device.

公开(公告)号：US20220103191A1

公开(公告)日：2022-03-31

申请号：US17125145

申请日：2020-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Shrikanth Ganapathy ,  John Kalamatianos

IPC: H03M13/35 ,  G06F11/10 ,  G06F12/0895

Abstract: Systems, apparatuses, and methods for implementing masked fault detection for reliable low voltage cache operation are disclosed. A processor includes a cache that can operate at a relatively low voltage level to conserve power. However, at low voltage levels, the cache is more likely to suffer from bit errors. To mitigate the bit errors occurring in cache lines at low voltage levels, the cache employs a strategy to uncover masked faults during runtime accesses to data by actual software applications. For example, on the first read of a given cache line, the data of the given cache line is inverted and written back to the same data array entry. Also, the error correction bits are regenerated for the inverted data. On a second read of the given cache line, if the fault population of the given cache line changes, then the given cache line's error protection level is updated.

公开(公告)号：US20210141740A1

公开(公告)日：2021-05-13

申请号：US16683142

申请日：2019-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Apostolos Kokolis ,  Shrikanth Ganapathy

IPC: G06F12/126 ,  G06F12/1027 ,  G06F12/0804

Abstract: A technique for accessing a memory having a high latency portion and a low latency portion is provided. The technique includes detecting a promotion trigger to promote data from the high latency portion to the low latency portion, in response to the promotion trigger, copying cache lines associated with the promotion trigger from the high latency portion to the low latency portion, and in response to a read request, providing data from either or both of the high latency portion or the low latency portion, based on a state associated with data in the high latency portion and the low latency portion.

公开(公告)号：US10884940B2

公开(公告)日：2021-01-05

申请号：US16230618

申请日：2018-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Shrikanth Ganapathy ,  Shomit Das ,  Matthew Tomei

IPC: G06F12/0893 ,  G06F11/07

Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

公开(公告)号：US20180302105A1

公开(公告)日：2018-10-18

申请号：US15489438

申请日：2017-04-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Shrikanth Ganapathy ,  Steven Raasch

IPC: H03M13/11 ,  H03M13/00 ,  G11C16/08 ,  G11C11/56

CPC classification number: G06F11/1064 ,  G11C29/42 ,  H03M13/19

Abstract: A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.