公开(公告)号：US11960854B2

公开(公告)日：2024-04-16

申请号：US17028723

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravinder Reddy Rachala ,  Stephen Victor Kosonocky ,  Miguel Rodriguez

IPC: G06F7/544 ,  H03K19/20 ,  H03K21/08

CPC classification number: G06F7/5443 ,  H03K21/08 ,  H03K19/20

Abstract: A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.

公开(公告)号：US20220206552A1

公开(公告)日：2022-06-30

申请号：US17134952

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky ,  Peter T. Hardman

IPC: G06F1/30 ,  G06F1/3203 ,  G05F1/565

Abstract: An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.

公开(公告)号：US20190296644A1

公开(公告)日：2019-09-26

申请号：US16440838

申请日：2019-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Miguel Rodriguez ,  Karthik Rao

IPC: H02M3/158 ,  G05F1/56 ,  G05F1/46 ,  G05F1/575

Abstract: An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

公开(公告)号：US20230145626A1

公开(公告)日：2023-05-11

申请号：US17521601

申请日：2021-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky ,  Kaushik Mazumdar

IPC: G01R31/40 ,  H03M3/00 ,  H03K5/24 ,  H03K19/0175

CPC classification number: G01R31/40 ,  H03M3/30 ,  H03K5/24 ,  H03K19/017509

Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.

公开(公告)号：US11619982B2

公开(公告)日：2023-04-04

申请号：US17134952

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky ,  Peter T. Hardman

IPC: G06F1/30 ,  G05F1/565 ,  G06F1/3203

Abstract: An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.

公开(公告)号：US11360541B2

公开(公告)日：2022-06-14

申请号：US17028692

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephen Victor Kosonocky ,  Miguel Rodriguez

IPC: G06F1/28 ,  G06F1/324 ,  H03K5/159 ,  G06F1/3296 ,  G06F1/08

Abstract: A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.

公开(公告)号：US11237220B2

公开(公告)日：2022-02-01

申请号：US16054576

申请日：2018-08-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravinder Reddy Rachala ,  Stephen Victor Kosonocky ,  Miguel Rodriguez

IPC: G01R31/40 ,  G11C27/02 ,  H03K17/687 ,  G06F1/3206 ,  H03K3/356 ,  G06F1/3296 ,  H03K3/03

Abstract: In one form, a power supply monitor including a current controlled oscillator circuit, a time-to-digital converter, and an output divider. The current controlled oscillator circuit has an input for receiving a power supply voltage to be measured, and an output for providing a frequency signal having a frequency linearly proportional to the power supply voltage. The time-to-digital converter has an input coupled to the output of the current controlled oscillator circuit, and an output for providing a count signal representative of a number of cycles of a reference clock signal per cycle of the frequency signal. The output divider has an input coupled to the output of the time-to-digital converter, and an output for providing a divided count signal representative of a value of the power supply voltage, and provides the divided count signal by dividing a fixed number by the count signal.

公开(公告)号：US10714152B1

公开(公告)日：2020-07-14

申请号：US16425579

申请日：2019-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky ,  Casey Lee Hardy

IPC: G11C5/14

Abstract: Systems, apparatuses, and methods for dynamically generating a memory bitcell supply voltage rail from a logic supply voltage rail are disclosed. A circuit includes at least one or more comparators, control logic, and power stage circuitry. The circuit receives a logic supply voltage rail and compares the logic supply voltage rail to threshold voltage(s) using the comparator(s). Comparison signal(s) from the comparator(s) are coupled to the control logic. The control logic generates mode control signals based on the comparison signal(s) and based on a programmable dynamic range that is desired for a memory bitcell supply voltage rail. The mode control signals are provided to the power stage circuitry which generates the memory bitcell supply voltage rail from the logic supply voltage rail. A voltage level of the memory bitcell supply voltage rail can be above, below, or the same as the logic supply voltage rail.

公开(公告)号：US20200041577A1

公开(公告)日：2020-02-06

申请号：US16054576

申请日：2018-08-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravinder Reddy Rachala ,  Stephen Victor Kosonocky ,  Miguel Rodriguez

IPC: G01R31/40 ,  G11C27/02 ,  H03K17/687 ,  H03K3/03 ,  H03K3/356 ,  G06F1/32

Abstract: In one form, a power supply monitor including a current controlled oscillator circuit, a time-to-digital converter, and an output divider. The current controlled oscillator circuit has an input for receiving a power supply voltage to be measured, and an output for providing a frequency signal having a frequency linearly proportional to the power supply voltage. The time-to-digital converter has an input coupled to the output of the current controlled oscillator circuit, and an output for providing a count signal representative of a number of cycles of a reference clock signal per cycle of the frequency signal. The output divider has an input coupled to the output of the time-to-digital converter, and an output for providing a divided count signal representative of a value of the power supply voltage, and provides the divided count signal by dividing a fixed number by the count signal.

公开(公告)号：US20160342166A1

公开(公告)日：2016-11-24

申请号：US14720385

申请日：2015-05-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky ,  Ravinder Reddy Rachala

IPC: G05F1/56

CPC classification number: G05F1/56 ,  G05F1/562 ,  G05F1/563 ,  G05F1/62 ,  H02M7/062 ,  H02M7/125

Abstract: A processor system includes first and second regulators for regulating an adjusted supply voltage. In one embodiment, the regulator system comprises a digital low-dropout (DLDO) control system comprising first and second regulators that generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value. The first regulator implements a first control loop and the second regulator implements a second and much faster acting control loop. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply.

Abstract translation: 处理器系统包括用于调节调整的电源电压的第一和第二调节器。 在一个实施例中，调节器系统包括数字低压差（DLDO）控制系统，该数字低压差（DLDO）控制系统包括第一和第二调节器，其产生多个控制信号以调节调整的电源电压，并且当下降水平低于下垂时产生电荷 阈值。 第一个调节器实现了第一个控制回路，第二个调节器实现了第二个更快速的控制回路。 为每个处理器核心提供了具有两个稳压器和控制回路的电源调节块，允许不同的内核根据一个共同的电源具有不同的稳压电源。