公开(公告)号：US20200212023A1

公开(公告)日：2020-07-02

申请号：US16236186

申请日：2018-12-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang-Yu LIN ,  Chi-Han CHEN ,  Chieh-Chen FU

IPC: H01L25/16 ,  H01L33/52 ,  H01L33/58 ,  H01L23/538

Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.

公开(公告)号：US20170047276A1

公开(公告)日：2017-02-16

申请号：US14825326

申请日：2015-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE ,  Chi-Han CHEN ,  Sheng-Chi HSIEH

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/11

Abstract: The present disclosure relates to a semiconductor device package and a method for manufacturing the same. The semiconductor device package comprises a substrate, a first patterned conductive layer, an insulator layer, a second patterned conductive layer, and a dielectric layer. The first patterned conductive layer is disposed on a surface of the substrate. The insulator layer is disposed on the surface of the substrate and covers the first patterned conductive layer. The second patterned conductive layer is fully encapsulated by the insulator layer. The dielectric layer is disposed on the insulator layer.

Abstract translation: 本公开涉及一种半导体器件封装及其制造方法。 半导体器件封装包括衬底，第一图案化导电层，绝缘体层，第二图案化导电层和电介质层。 第一图案化导电层设置在基板的表面上。 绝缘体层设置在衬底的表面上并覆盖第一图案化导电层。 第二图案化导电层被绝缘体层完全封装。 电介质层设置在绝缘体层上。

公开(公告)号：US20160233292A1

公开(公告)日：2016-08-11

申请号：US14618822

申请日：2015-02-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi-Han CHEN

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L24/26 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure comprises a first dielectric layer, a die pad, an active component, at least one first metal bar, at least one second metal bar and a through via. The first dielectric layer has a first surface and a second surface opposite to the first surface. The die pad is located within the first dielectric layer. The active component is located within the first dielectric layer and disposed on the die pad. The first metal bar is disposed on the first surface of the first dielectric layer, and electrically connected to the active component. The second metal bar is disposed on the second surface of the first dielectric layer. The through via penetrates the first dielectric layer and connects the at least one first metal bar to the at least one second metal bar.

Abstract translation: 本公开涉及一种半导体封装结构及其制造方法。 半导体封装结构包括第一介电层，管芯焊盘，有源部件，至少一个第一金属条，至少一个第二金属条和通孔。 第一电介质层具有与第一表面相对的第一表面和第二表面。 芯片焊盘位于第一介电层内。 有源部件位于第一电介质层内并且设置在管芯焊盘上。 第一金属棒设置在第一介电层的第一表面上，并与有源元件电连接。 第二金属棒设置在第一介电层的第二表面上。 通孔穿过第一电介质层并将至少一个第一金属棒连接到至少一个第二金属棒。