公开(公告)号：US20230393194A1

公开(公告)日：2023-12-07

申请号：US18236930

申请日：2023-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao WANG ,  Tsung-Tang TSAI ,  Chih-Yi HUANG

IPC: G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L23/00

CPC classification number: G01R31/2896 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/552 ,  H01L25/18 ,  H01L24/16 ,  H01L21/563

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

公开(公告)号：US20210233836A1

公开(公告)日：2021-07-29

申请号：US16942579

申请日：2020-07-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang LIU ,  Tsung-Tang TSAI ,  Huang-Hsien CHANG ,  Ching-Ju CHEN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L21/48

Abstract: A substrate structure includes a wiring structure, a first bump pad, a second bump pad and a compensation structure. The wiring structure includes a plurality of redistribution layers. The first bump pad and the second bump pad are bonded to and electrically connected to the wiring structure. An amount of redistribution layers disposed under the first bump pad is greater than an amount of redistribution layers disposed under the second bump pad. The compensation structure is disposed under the second bump pad.

公开(公告)号：US20210104595A1

公开(公告)日：2021-04-08

申请号：US17102258

申请日：2020-11-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Syu-Tang LIU ,  Huang-Hsien CHANG ,  Tsung-Tang TSAI ,  Hung-Jung TU

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/285

Abstract: A vertical capacitor structure includes a substrate, at least a pillar, a first conductive layer, a first dielectric layer and a second conductive layer. The substrate defines a cavity. The pillar is disposed in the cavity. The first conductive layer covers and is conformal to the cavity of the substrate and the pillar, and is insulated from the substrate. The first dielectric layer covers and is conformal to the first conductive layer. The second conductive layer covers and is conformal to the first dielectric layer. The first conductive layer, the first dielectric layer and the second conductive layer jointly form a capacitor component.