公开(公告)号：US08156362B2

公开(公告)日：2012-04-10

申请号：US12198974

申请日：2008-08-27

申请人： Alexander Branover ,  Frank Helms ,  Maurice Steinman

发明人： Alexander Branover ,  Frank Helms ,  Maurice Steinman

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/329 ,  Y02D10/24

摘要： A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

摘要翻译： 与包括一个或多个核心的处理器连接的电源管理控制器（PMC）。 PMC可以被配置为与每个相应的核心通信，使得由相应的处理器核心执行的微代码可以识别什么时候进行请求以将各个核心转换到目标功率状态。 对于每个相应的核心，状态监视器可以监视与相应核心的相关联的活动状态驻留，非活动状态驻留，直接存储器访问（DMA）传送活动，与相应核心相关联的输入/输出（I / O）过程 ，以及与相应核心相关联的定时器 - 刻度（TT）间隔的值。 状态监视器可以基于监视导出各个核心的各自的状态信息，并且指示是否应允许相应的核心转换到对应的目标功率状态。 PMC可以相应地将相应的处理器核心转变到相应的目标功率状态。

公开(公告)号：US08028185B2

公开(公告)日：2011-09-27

申请号：US12045764

申请日：2008-03-11

申请人： Alexander Branover ,  Rajen S. Ramchandani

发明人： Alexander Branover ,  Rajen S. Ramchandani

IPC分类号： G06F1/00

CPC分类号： G06F1/3203

摘要： A processor may comprise one or more cores, where each respective core may comprise one or more state registers, and non-volatile memory configured to store microcode instructions executed by the respective processor core. The processor may further comprise a power management controller (PMC) interfacing with each respective core, and a state monitor (SM) interfacing with the PMC. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a low-power state. The microcode may communicate the request to the PMC, which may in turn determine if the request is for the respective core to transition to a zero-power state. If it is, the PMC may communicate with the SM to determine whether to transition the respective processor core to the zero-power state, and initiate transition to the zero-power state if a determination to transition to the zero-power state is made.

摘要翻译： 处理器可以包括一个或多个核，其中每个相应的核可以包括一个或多个状态寄存器，以及被配置为存储由相应的处理器核执行的微代码指令的非易失性存储器。 处理器还可以包括与每个相应核心接口的功率管理控制器（PMC）以及与PMC接口的状态监视器（SM）。 PMC可以被配置为与每个相应的核心进行通信，使得由相应的处理器核心执行的微代码可以识别何时请求将相应的核心转换到低功率状态。 微码可以将该请求传送到PMC，PMC可以依次确定该请求是否为相应的核心转换到零功率状态。 如果是，则PMC可以与SM进行通信，以确定是否将相应的处理器核心转换到零功率状态，并且如果做出转变到零功率状态的确定，则启动到零功率状态的转变。

公开(公告)号：US20110022356A1

公开(公告)日：2011-01-27

申请号：US12508902

申请日：2009-07-24

申请人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

发明人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

IPC分类号： G06F15/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3006 ,  G06F11/3024 ,  G06F11/3058 ,  G06F11/3079 ,  G06F11/3433 ,  G06F2201/885 ,  Y02D10/126 ,  Y02D10/172

摘要： Performance sensitivities to a change in performance capabilities of computational units of a computer system are determined based on measured utilization metrics for each of the computational units. In order to determine the performance sensitivities, in one approach, the computational units are operated at a first performance level, and respective first utilization metrics are determined. The computational units are then operated at a second performance level and respective second utilization metrics are determined. The sensitivity to performance capability change, e.g., a frequency change, is determined based on the respective first and second utilization metrics. The performance sensitivities of the computational units to a change in performance capability are continually updated in response to, e.g., a process context change of a computational unit or in response to a predetermined period of time elapsing since the last sensitivity to a performance capability change was determined for a computational unit.

摘要翻译： 基于用于每个计算单元的测量的利用度量确定对计算机系统的计算单元的性能能力变化的性能敏感度。 为了确定性能灵敏度，在一种方法中，计算单元在第一性能水平下操作，并且确定各自的第一使用度量。 然后，计算单元在第二性能水平下操作并确定相应的第二利用度量。 基于相应的第一和第二利用度量来确定对性能能力改变的敏感性，例如频率变化。 响应于例如计算单元的处理上下文变化或响应于经过的预定时间段，持续地更新计算单元对性能能力变化的性能敏感度，因为对性能能力变化的最后敏感度为 确定一个计算单位。

公开(公告)号：US20100058078A1

公开(公告)日：2010-03-04

申请号：US12254650

申请日：2008-10-20

申请人： Alexander Branover ,  Frank P. Helms ,  John P. Petry ,  Maurice B. Steinman

发明人： Alexander Branover ,  Frank P. Helms ,  John P. Petry ,  Maurice B. Steinman

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/329 ,  Y02D10/24

摘要： A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.

摘要翻译： 系统可以包括多个处理单元，以及与处理单元接口的控制单元和监控单元。 控制单元可以接收将处理单元转换到各个目标功率状态的请求，并且指定与各个目标功率状态相对应的各个目标HW功率状态。 监视单元可以监视系统的操作特性，并且基于操作特性确定是否允许处理单元转换到相应的目标硬件（HW）功率状态。 控制单元可以被配置为针对确定不应该允许转换到其各自的目标HW功率状态的每个处理单元，将相应的目标HW功率状态改变到相应的更新的HW功率状态。 控制单元还可以被配置为当多个处理的子集的处理单元时，基于多个处理单元的子集的处理单元的各个目标HW功率状态来推断公共目标HW功率状态 单位共享至少一个资源域。

公开(公告)号：US5040652A

公开(公告)日：1991-08-20

申请号：US349358

申请日：1989-05-09

申请人： Aaron M. Fish ,  Alexander Branover ,  Zgorzak Leszek

发明人： Aaron M. Fish ,  Alexander Branover ,  Zgorzak Leszek

IPC分类号： E05B55/14 ,  E05B13/00 ,  E05B15/00 ,  E05B17/00 ,  E05C1/16

CPC分类号： E05C1/163 ,  E05B17/0058 ,  E05B13/004 ,  E05B13/005 ,  Y10T70/5416 ,  Y10T70/5677 ,  Y10T70/5805 ,  Y10T70/7751 ,  Y10T70/7949

摘要： A permutation lock chamber has a chamber shaft extending therethrough which is held against rotation when the chamber is in a locked condition and which is rotatable when the chamber is in an unlocked condition. The chamber shaft is connected to the shaft of an outer door handle through a clutch. When the chamber is in its unlock condition and the outer door handle is rotated, the clutch engages and the chamber shaft rotates with the outer door handle shaft. When the chamber is in its locked condition and the outer door handle is rotated, the clutch slips to permit rotation of the outer door handle shaft without rotation of the chamber shaft.

公开(公告)号：US08862920B2

公开(公告)日：2014-10-14

申请号：US13162425

申请日：2011-06-16

申请人： Alexander Branover ,  Maurice B. Steinman

发明人： Alexander Branover ,  Maurice B. Steinman

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/151

摘要： A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state.

摘要翻译： 调节处理系统中的功率状态的方法可以从将当前处理器功率状态报告给输入 - 输出集线器的处理器组件开始，其中当前处理器功率状态对应于多个不同的处理器功率状态中的一个， 状态为非活动状态。 输入 - 输出集线器接收指示当前处理器功率状态的数据，并且响应于接收到当前处理器功率状态，建立对应于多个不同集线器功率状态中的一个的最低可允许集线器功率状态，该状态从活动状态 到非活动状态。 该方法通过确定用于输入 - 输出集线器的当前集线器功率状态来继续，其中当前集线器功率状态的深度小于或等于最低可允许集线器功率状态的深度。

公开(公告)号：US08589629B2

公开(公告)日：2013-11-19

申请号：US12413124

申请日：2009-03-27

申请人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

发明人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0888

摘要： A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.

摘要翻译： 预期在计算系统的共享高速缓冲存储器中进行数据分配的系统和方法。 共享组相关高速缓存的每个缓存方式可以被多个源访问，诸如一个或多个处理器核，图形处理单元（GPU），输入/输出（I / O）设备或多个不同的软件线程。 共享高速缓存控制器基于所接收的存储器请求的相应源，启用或禁用对每个高速缓存路径的访问。 一个或多个配置和状态寄存器（CSR）存储用于改变对每个共享缓存方式的可访问性的编码值。 可以通过改变CSR中的存储值来控制共享缓存方式的可访问性，以在共享高速缓存内创建伪RAM结构，并且在断电序列期间逐渐减小共享高速缓存的大小，而共享高速缓存共享 缓存继续运行。

公开(公告)号：US08443209B2

公开(公告)日：2013-05-14

申请号：US12508935

申请日：2009-07-24

申请人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

发明人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

IPC分类号： G05B13/02 ,  G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

摘要： A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.

摘要翻译： 功率分配策略根据多个计算单元中的每个计算单元的性能灵敏度来限制计算机系统中的多个计算单元的子集的性能，以改变性能能力，例如频率变化。 计算单元子集的性能可以通过设置子集可以被操作的功率状态和/或将该子集的当前功率状态降低到较低功率状态来限制。 其性能受限的子集包括根据存储的灵敏度数据对性能敏感度最低的计算单元。 子集可以包括一个或多个处理核心，并且一个或多个处理核心的性能可能受到响应于被执行的CPU限制的应用程序或图形处理单元（GPU）绑定应用程序的限制。

公开(公告)号：US08112647B2

公开(公告)日：2012-02-07

申请号：US12254650

申请日：2008-10-20

申请人： Alexander Branover ,  Frank P. Helms ,  John P. Petry ,  Maurice B. Steinman

发明人： Alexander Branover ,  Frank P. Helms ,  John P. Petry ,  Maurice B. Steinman

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/329 ,  Y02D10/24

摘要： A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.

摘要翻译： 系统可以包括多个处理单元，以及与处理单元接口的控制单元和监控单元。 控制单元可以接收将处理单元转换到各个目标功率状态的请求，并且指定与各个目标功率状态相对应的各个目标HW功率状态。 监视单元可以监视系统的操作特性，并且基于操作特性确定是否允许处理单元转换到相应的目标硬件（HW）功率状态。 控制单元可以被配置为针对确定不应该允许转换到其各自的目标HW功率状态的每个处理单元，将相应的目标HW功率状态改变到相应的更新的HW功率状态。 控制单元还可以被配置为当多个处理的子集的处理单元时，基于多个处理单元的子集的处理单元的各个目标HW功率状态来推断公共目标HW功率状态 单位共享至少一个资源域。

公开(公告)号：US20110112798A1

公开(公告)日：2011-05-12

申请号：US12623997

申请日：2009-11-23

申请人： Alexander Branover ,  Maurice B. Steinman ,  Jonathan D. Hauke ,  Jonathan M. Owen

发明人： Alexander Branover ,  Maurice B. Steinman ,  Jonathan D. Hauke ,  Jonathan M. Owen

IPC分类号： G21C17/00

CPC分类号： G06F12/0808 ,  G06F1/3203 ,  G06F12/0831 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13

摘要： A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states.

摘要翻译： 处理节点跟踪与其内部缓存或存储器系统相关联的探测活动级别。 如果探测器活动级别增加到阈值探测器活动级别以上，则处理节点的性能状态将增加到其当前的性能状态以提供增强的响应探测请求的性能能力。 响应于探测器活动级别高于阈值探测器活动级别而进入更高性能状态之后，处理节点响应于探测活动的减少而返回到较低的性能状态。 可能存在多个阈值探测活动级别和相关的性能状态。