公开(公告)号：US08909866B2

公开(公告)日：2014-12-09

申请号：US13669502

申请日：2012-11-06

申请人： John Kalamatianos ,  Ravindra Nath Bhargava ,  Ramkumar Jayaseelan

发明人： John Kalamatianos ,  Ravindra Nath Bhargava ,  Ramkumar Jayaseelan

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0897

摘要： A processor transfers prefetch requests from their targeted cache to another cache in a memory hierarchy based on a fullness of a miss address buffer (MAB) or based on confidence levels of the prefetch requests. Each cache in the memory hierarchy is assigned a number of slots at the MAB. In response to determining the fullness of the slots assigned to a cache is above a threshold when a prefetch request to the cache is received, the processor transfers the prefetch request to the next lower level cache in the memory hierarchy. In response, the data targeted by the access request is prefetched to the next lower level cache in the memory hierarchy, and is therefore available for subsequent provision to the cache. In addition, the processor can transfer a prefetch request to lower level caches based on a confidence level of a prefetch request.

摘要翻译： 处理器根据缺失地址缓冲区（MAB）的丰满度或基于预取请求的置信水平，将预取请求从目标缓存传输到存储器层次结构中的另一高速缓存。 内存层次结构中的每个高速缓存在MAB上分配了多个插槽。 响应于当接收到高速缓存的预取请求时，分配给高速缓存的时隙的丰满度高于阈值，则处理器将预取请求传送到存储器层级中的下一个较低级别的高速缓存。 作为响应，访问请求所针对的数据被预取到存储器层次结构中的下一个较低级缓存，因此可用于后续的缓存提供。 此外，处理器可以基于预取请求的置信水平将预取请求传送到较低级别的高速缓存。

公开(公告)号：US08443209B2

公开(公告)日：2013-05-14

申请号：US12508935

申请日：2009-07-24

申请人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

发明人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

IPC分类号： G05B13/02 ,  G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

摘要： A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.

摘要翻译： 功率分配策略根据多个计算单元中的每个计算单元的性能灵敏度来限制计算机系统中的多个计算单元的子集的性能，以改变性能能力，例如频率变化。 计算单元子集的性能可以通过设置子集可以被操作的功率状态和/或将该子集的当前功率状态降低到较低功率状态来限制。 其性能受限的子集包括根据存储的灵敏度数据对性能敏感度最低的计算单元。 子集可以包括一个或多个处理核心，并且一个或多个处理核心的性能可能受到响应于被执行的CPU限制的应用程序或图形处理单元（GPU）绑定应用程序的限制。

公开(公告)号：US20110022356A1

公开(公告)日：2011-01-27

申请号：US12508902

申请日：2009-07-24

申请人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

发明人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

IPC分类号： G06F15/00

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3006 ,  G06F11/3024 ,  G06F11/3058 ,  G06F11/3079 ,  G06F11/3433 ,  G06F2201/885 ,  Y02D10/126 ,  Y02D10/172

摘要： Performance sensitivities to a change in performance capabilities of computational units of a computer system are determined based on measured utilization metrics for each of the computational units. In order to determine the performance sensitivities, in one approach, the computational units are operated at a first performance level, and respective first utilization metrics are determined. The computational units are then operated at a second performance level and respective second utilization metrics are determined. The sensitivity to performance capability change, e.g., a frequency change, is determined based on the respective first and second utilization metrics. The performance sensitivities of the computational units to a change in performance capability are continually updated in response to, e.g., a process context change of a computational unit or in response to a predetermined period of time elapsing since the last sensitivity to a performance capability change was determined for a computational unit.

摘要翻译： 基于用于每个计算单元的测量的利用度量确定对计算机系统的计算单元的性能能力变化的性能敏感度。 为了确定性能灵敏度，在一种方法中，计算单元在第一性能水平下操作，并且确定各自的第一使用度量。 然后，计算单元在第二性能水平下操作并确定相应的第二利用度量。 基于相应的第一和第二利用度量来确定对性能能力改变的敏感性，例如频率变化。 响应于例如计算单元的处理上下文变化或响应于经过的预定时间段，持续地更新计算单元对性能能力变化的性能敏感度，因为对性能能力变化的最后敏感度为 确定一个计算单位。

公开(公告)号：US20100281231A1

公开(公告)日：2010-11-04

申请号：US12431874

申请日：2009-04-29

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F12/00 ,  G06F9/46

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US20090083741A1

公开(公告)日：2009-03-26

申请号：US11859044

申请日：2007-09-21

申请人： Guhan Krishnan ,  John Kalamatianos

发明人： Guhan Krishnan ,  John Kalamatianos

IPC分类号： G06F9/46

CPC分类号： G06F9/5016

摘要： A technique of accessing a resource includes receiving, at a master scheduler, resource access requests. The resource access requests are translated into respective slave state machine work orders that each include one or more respective commands. The respective commands are assigned, for execution, to command streams associated with respective slave state machines. The respective commands are then executed responsive to the respective slave state machines.

摘要翻译： 访问资源的技术包括在主调度器处接收资源访问请求。 资源访问请求被转换成各自的从状态机工作单，其各自包括一个或多个相应的命令。 相应的命令被分配用于执行以命令与相应从属状态机相关联的流。 然后响应于相应的从状态机执行各自的命令。

公开(公告)号：US08645639B2

公开(公告)日：2014-02-04

申请号：US13600614

申请日：2012-08-31

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F13/18

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US08266389B2

公开(公告)日：2012-09-11

申请号：US12431874

申请日：2009-04-29

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F13/18

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US08341344B2

公开(公告)日：2012-12-25

申请号：US11859044

申请日：2007-09-21

申请人： Guhan Krishnan ,  John Kalamatianos

发明人： Guhan Krishnan ,  John Kalamatianos

IPC分类号： G06F12/00 ,  G06F9/46

CPC分类号： G06F9/5016

摘要： A technique of accessing a resource includes receiving, at a master scheduler, resource access requests. The resource access requests are translated into respective slave state machine work orders that each include one or more respective commands. The respective commands are assigned, for execution, to command streams associated with respective slave state machines. The respective commands are then executed responsive to the respective slave state machines.

摘要翻译： 访问资源的技术包括在主调度器处接收资源访问请求。 资源访问请求被转换成各自的从状态机工作单，其各自包括一个或多个相应的命令。 相应的命令被分配用于执行以命令与相应从属状态机相关联的流。 然后响应于相应的从状态机执行各自的命令。

公开(公告)号：US20110283124A1

公开(公告)日：2011-11-17

申请号：US12777657

申请日：2010-05-11

申请人： Alexander Branover ,  Norman M. Hack ,  Maurice B. Steinman ,  John Kalamatianos ,  Jonathan M. Owen

发明人： Alexander Branover ,  Norman M. Hack ,  Maurice B. Steinman ,  John Kalamatianos ,  Jonathan M. Owen

IPC分类号： G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

摘要翻译： 公开了一种用于动态控制高速缓存大小的方法和装置。 在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。 该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

公开(公告)号：US20110022857A1

公开(公告)日：2011-01-27

申请号：US12508935

申请日：2009-07-24

申请人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

发明人： Sebastien Nussbaum ,  Alexander Branover ,  John Kalamatianos

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

摘要： A power allocation strategy limits performance of a subset of a plurality of computational units in a computer system according to performance sensitivity of each of the plurality of computational units to a change performance capability, e.g., frequency change. The performance of the subset of computational units may be limited by setting a power state in which the subset may be operated and/or reducing a current power state of the subset to a lower power state. The subset whose performance is limited includes computational units that are least performance sensitive according to stored sensitivity data. The subset may include one or more processing cores and performance of the one or more processing cores may be limited in response to a CPU-bounded application or graphics processing unit (GPU)-bounded application being executed.

摘要翻译： 功率分配策略根据多个计算单元中的每个计算单元的性能灵敏度来限制计算机系统中的多个计算单元的子集的性能，以改变性能能力，例如频率变化。 计算单元子集的性能可以通过设置子集可以被操作的功率状态和/或将该子集的当前功率状态降低到较低功率状态来限制。 其性能受限的子集包括根据存储的灵敏度数据对性能敏感度最低的计算单元。 子集可以包括一个或多个处理核心，并且一个或多个处理核心的性能可能受到响应于被执行的CPU限制的应用程序或图形处理单元（GPU）绑定应用程序的限制。