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    Hardware monitoring and decision making for transitioning in and out of low-power state
    1.
    发明授权
    Hardware monitoring and decision making for transitioning in and out of low-power state 有权
    硬件监控和决策过渡进出低功耗状态

    公开(公告)号：US08156362B2

    公开(公告)日：2012-04-10

    申请号：US12198974

    申请日：2008-08-27

    申请人： Alexander Branover ,  Frank Helms ,  Maurice Steinman

    发明人： Alexander Branover ,  Frank Helms ,  Maurice Steinman

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/329 ,  Y02D10/24

    摘要： A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

    摘要翻译： 与包括一个或多个核心的处理器连接的电源管理控制器（PMC）。 PMC可以被配置为与每个相应的核心通信，使得由相应的处理器核心执行的微代码可以识别什么时候进行请求以将各个核心转换到目标功率状态。 对于每个相应的核心，状态监视器可以监视与相应核心的相关联的活动状态驻留，非活动状态驻留，直接存储器访问（DMA）传送活动，与相应核心相关联的输入/输出（I / O）过程 ，以及与相应核心相关联的定时器 - 刻度（TT）间隔的值。 状态监视器可以基于监视导出各个核心的各自的状态信息，并且指示是否应允许相应的核心转换到对应的目标功率状态。 PMC可以相应地将相应的处理器核心转变到相应的目标功率状态。

    Hardware Monitoring and Decision Making for Transitioning In and Out of Low-Power State
    2.
    发明申请
    Hardware Monitoring and Decision Making for Transitioning In and Out of Low-Power State 有权
    硬件监控和决策过渡进出低功耗状态

    公开(公告)号：US20090235105A1

    公开(公告)日：2009-09-17

    申请号：US12198974

    申请日：2008-08-27

    申请人： Alexander Branover ,  Frank Helms ,  Maurice Steinman

    发明人： Alexander Branover ,  Frank Helms ,  Maurice Steinman

    IPC分类号： G06F1/26 ,  G06F13/28 ,  G06F13/24

    CPC分类号： G06F1/3203 ,  G06F1/3246 ,  G06F1/329 ,  Y02D10/24

    摘要： A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

    摘要翻译： 与包括一个或多个核心的处理器连接的电源管理控制器（PMC）。 PMC可以被配置为与每个相应的核心通信，使得由相应的处理器核心执行的微代码可以识别什么时候进行请求以将各个核心转换到目标功率状态。 对于每个相应的核心，状态监视器可以监视与相应核心的相关联的活动状态驻留，非活动状态驻留，直接存储器访问（DMA）传送活动，与相应核心相关联的输入/输出（I / O）过程 ，以及与相应核心相关联的定时器 - 刻度（TT）间隔的值。 状态监视器可以基于监视导出各个核心的各自的状态信息，并且指示是否应允许相应的核心转换到对应的目标功率状态。 PMC可以相应地将相应的处理器核心转变到相应的目标功率状态。

    DYNAMIC PERFORMANCE CONTROL OF PROCESSING NODES
    5.
    发明申请
    DYNAMIC PERFORMANCE CONTROL OF PROCESSING NODES 有权
    加工过程动态性能控制

    公开(公告)号：US20120054519A1

    公开(公告)日：2012-03-01

    申请号：US12868996

    申请日：2010-08-26

    申请人： Alexander Branover ,  Maurice Steinman ,  William L. Bircher

    发明人： Alexander Branover ,  Maurice Steinman ,  William L. Bircher

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3215 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.

    摘要翻译： 公开了一种用于处理节点的性能控制的装置和方法。 在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点 时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使 处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。

    Method and apparatus for demand-based control of processing node performance
    6.
    发明授权
    Method and apparatus for demand-based control of processing node performance 有权
    用于基于需求的处理节点性能控制的方法和装置

    公开(公告)号：US08484498B2

    公开(公告)日：2013-07-09

    申请号：US12868996

    申请日：2010-08-26

    申请人： Alexander Branover ,  Maurice Steinman ,  William L. Bircher

    发明人： Alexander Branover ,  Maurice Steinman ,  William L. Bircher

    IPC分类号： G06F1/00 ,  G06F1/32

    CPC分类号： G06F1/3215 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.

    摘要翻译： 公开了一种用于处理节点的性能控制的装置和方法。 在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使得处理节点在连续的连续操作期间在高操作点 时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使 处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。

    FUNCTION BASED DYNAMIC POWER CONTROL
    8.
    发明申请
    FUNCTION BASED DYNAMIC POWER CONTROL 有权
    基于功能的动态功率控制

    公开(公告)号：US20120102344A1

    公开(公告)日：2012-04-26

    申请号：US12909006

    申请日：2010-10-21

    申请人： Andrej Kocev ,  Alexander Branover

    发明人： Andrej Kocev ,  Alexander Branover

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3237 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

    摘要： A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.

    摘要翻译： 公开了一种用于基于动态功能的功率控制的系统和方法。 在一个实施例中，系统包括具有存储器控制器和耦合到存储器控制器的通信集线器的桥接单元。 该系统还包括电力管理单元，其中电力管理单元被配置为响应于确定多个处理器核心中的每一个处于空闲状态并且I / O接口单元已经空闲而对通信集线器进行时钟门 超过第一阈值的时间量。 电源管理单元还被配置为响应于时钟门控通信集线器来对存储器控制器进行时钟门控，并且确定耦合到存储器控制器的存储器处于第一低功率状态。 功率管理单元还可以在其门控门控之后执行功能单元的功率门控。

    MECHANISM FOR VOLTAGE REGULATOR LOAD LINE COMPENSATION USING MULTIPLE VOLTAGE SETTINGS PER OPERATING STATE
    9.
    发明申请
    MECHANISM FOR VOLTAGE REGULATOR LOAD LINE COMPENSATION USING MULTIPLE VOLTAGE SETTINGS PER OPERATING STATE 有权
    运行状态下使用多个电压设置的电压调节器负载线补偿机制

    公开(公告)号：US20120054515A1

    公开(公告)日：2012-03-01

    申请号：US12872414

    申请日：2010-08-31

    申请人： Samuel D. Naffziger ,  Alexander Branover

    发明人： Samuel D. Naffziger ,  Alexander Branover

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

    摘要： A system includes one or more processor cores, and a voltage regulator that provides an operating voltage to the one or more processor cores in response to receiving a voltage identifier signal that is indicative of the operating voltage. The system also includes a power management unit that may provide a first voltage identifier signal corresponding to a first operating voltage in response to determining that the processor cores are operating in a first operating state in which the one or more processor cores may draw up to a maximum load current. The power management unit may also provide a second voltage identifier signal corresponding to a second operating voltage, which is less than the first operating voltage, in response to determining that the processor cores are operating in a second operating state in which the processor cores are incapable of an increase in load current above a predetermined amount.

    摘要翻译： 系统包括一个或多个处理器核心和电压调节器，其响应于接收到指示工作电压的电压标识符信号而向一个或多个处理器核心提供工作电压。 该系统还包括功率管理单元，其可以响应于确定处理器核在第一操作状态下操作而提供与第一工作电压相对应的第一电压标识符信号，其中一个或多个处理器核可以绘制到 最大负载电流。 电源管理单元还可以响应于确定处理器核在其中处理器核不能够处于第二操作状态的操作而提供对应于小于第一工作电压的第二工作电压的第二电压标识符信号 负载电流的增加高于预定量。

    Cache flush based on idle prediction and probe activity level
    10.
    发明授权
    Cache flush based on idle prediction and probe activity level 有权
    基于空闲预测和探测活动级别的缓存刷新

    公开(公告)号：US09021209B2

    公开(公告)日：2015-04-28

    申请号：US12702085

    申请日：2010-02-08

    申请人： Alexander Branover ,  Maurice B. Steinman

    发明人： Alexander Branover ,  Maurice B. Steinman

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0808 ,  G06F1/3203 ,  G06F12/0831 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13

    摘要： A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.

    摘要翻译： 处理节点跟踪与其高速缓存相关联的探测活动级别。 处理节点和/或处理系统进一步预测空闲持续时间。 如果探测器活动级别增加到高于阈值探测器活动级别，并且空闲持续时间预测高于阈值空闲持续时间阈值，则处理节点刷新其高速缓存以防止对高速缓存的探测。 如果探测器活动级别高于阈值探测器活动级别，但是预测的空闲持续时间太短，则处理节点的性能状态增加到高于其当前性能状态，以提供响应探测请求的增强的性能能力。