公开(公告)号：US12164445B1

公开(公告)日：2024-12-10

申请号：US17592233

申请日：2022-02-03

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Itai Avron ,  Adi Habusha ,  Aviv Bakal ,  Leonid Froenchenko

IPC: G06F13/00 ,  G06F13/16

Abstract: The coherency of data can be maintained even for accelerators that may not directly support, or be part of, a coherency protocol or domain. A pair of agents can be utilized that include an application accelerator agent and a coherent agent. The coherent agent can support the coherency protocol and track coherency information for data in the coherency environment, to ensure coherent access to the data. The application accelerator agent can work with the coherent agent to obtain the data according to the coherency protocol, then perform operations on the data corresponding to a respective application or process. Such an approach enables an accelerator to function like a processor or processor core that otherwise supports the coherency protocol and is part of the coherency domain. A single coherent agent can be used to maintain coherency information for multiple other components or agents.

公开(公告)号：US11868204B1

公开(公告)日：2024-01-09

申请号：US17548270

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Osnat Katz ,  Nir Bar-Or ,  Adi Habusha

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751

Abstract: A system includes an obsolete cache-line vector having a plurality of memory elements, wherein each memory element has a one-to-one correspondence to a cache line entry of a cache memory. The vector can capture cache line errors that occur at different times from an error detection logic associated with the cache memory. A counter can be coupled to the obsolete cache-line vector for tracking how many of the memory elements in the vector are activated. When a predetermined threshold is reached, a threshold comparator can release a trigger for further analysis. An error events logger can be used to track all of the errors that occurred. The error events logger can also use a time stamp, which can assist the RAS system in analyzing a correlation between the errors, such as patterns that occur and time differences between the errors.

公开(公告)号：US11809349B1

公开(公告)日：2023-11-07

申请号：US17304240

申请日：2021-06-16

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Itai Avron ,  Tzachi Zidenberg ,  Ofer Naaman

IPC: G06F13/24 ,  G06F11/07 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F11/0712 ,  G06F2009/45579 ,  G06F2201/815 ,  G06F2213/24

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

公开(公告)号：US20230007106A1

公开(公告)日：2023-01-05

申请号：US17930696

申请日：2022-09-08

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L69/22 ,  H04L49/90 ,  H04L49/60 ,  H04L45/00 ,  H04L45/74 ,  H04L47/2425 ,  H04L47/10 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/13 ,  G06F16/90 ,  G06F16/25 ,  G06F16/2458 ,  G06F16/903 ,  H04L69/00 ,  H04L69/12 ,  H04L69/16

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

公开(公告)号：US20190364136A1

公开(公告)日：2019-11-28

申请号：US16435266

申请日：2019-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L29/06 ,  H04L12/851 ,  H04L12/801

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result

公开(公告)号：US20230283696A1

公开(公告)日：2023-09-07

申请号：US18316126

申请日：2023-05-11

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L69/22 ,  H04L49/90 ,  H04L49/60 ,  H04L45/00 ,  H04L45/74 ,  H04L47/2425 ,  H04L47/10 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/13 ,  G06F16/90 ,  G06F16/25 ,  G06F16/2458 ,  G06F16/903 ,  H04L69/00 ,  H04L69/12 ,  H04L69/16

CPC classification number: H04L69/22 ,  H04L49/90 ,  H04L49/602 ,  H04L45/38 ,  H04L45/74 ,  H04L47/2433 ,  H04L47/10 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/134 ,  G06F16/90 ,  G06F16/254 ,  G06F16/2471 ,  G06F16/90344 ,  H04L69/02 ,  H04L69/12 ,  H04L69/16 ,  H04L1/0066

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

公开(公告)号：US11677866B2

公开(公告)日：2023-06-13

申请号：US17930696

申请日：2022-09-08

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L69/22 ,  H04L49/90 ,  H04L49/60 ,  H04L45/00 ,  H04L45/74 ,  H04L47/2425 ,  H04L47/10 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/13 ,  G06F16/90 ,  G06F16/25 ,  G06F16/2458 ,  G06F16/903 ,  H04L69/00 ,  H04L69/12 ,  H04L69/16 ,  H04L1/00 ,  G06F9/30 ,  G06F13/38 ,  H04L47/125

CPC classification number: H04L69/22 ,  G06F16/00 ,  G06F16/134 ,  G06F16/182 ,  G06F16/245 ,  G06F16/2471 ,  G06F16/254 ,  G06F16/90 ,  G06F16/90344 ,  H04L45/38 ,  H04L45/74 ,  H04L47/10 ,  H04L47/2433 ,  H04L49/602 ,  H04L49/90 ,  H04L69/02 ,  H04L69/12 ,  H04L69/16 ,  G06F9/3001 ,  G06F13/385 ,  H04L1/0066 ,  H04L47/125 ,  Y02D10/00

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

公开(公告)号：US11445051B2

公开(公告)日：2022-09-13

申请号：US17247147

申请日：2020-12-01

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L69/22 ,  H04L49/90 ,  H04L49/60 ,  H04L45/00 ,  H04L45/74 ,  H04L47/2425 ,  H04L47/10 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/13 ,  G06F16/90 ,  G06F16/25 ,  G06F16/2458 ,  G06F16/903 ,  H04L69/00 ,  H04L69/12 ,  H04L69/16 ,  H04L1/00 ,  G06F9/30 ,  G06F13/38 ,  H04L47/125

Abstract: A packet processing technique can include selecting a protocol field from the packet, and performing a comparison of the selected protocol field with comparison data in a compare logic array to output a protocol index. The protocol index can be used as an address to read parsing commands from a parse control table, and a parse result can be generated based on executing the parsing commands on the packet. The parse results are used to derive a parse result vector, which can be used by a forwarding engine to forward the packet.