Thread offset counter
    11.
    发明授权

    公开(公告)号:US09697005B2

    公开(公告)日:2017-07-04

    申请号:US14096580

    申请日:2013-12-04

    Inventor: Boris Lerner

    Abstract: In an example, there is disclosed a digital signal processor having a register containing a modular integer configured for use as a thread offset counter. In a multi-stage, pipelined loop, which may be implemented in microcode, the main body of the loop has only one repeating stage. On each stage, the operation executed by each thread of the single repeating stage is identified by the sum of a fixed integer and the thread offset counter. After each pass through the loop, the thread offset counter is incremented, thus maintaining pipelined operation of the single repeating stage.

    Optical system for determining interferer locus among two or more regions of a transmissive liquid crystal structure

    公开(公告)号:US11320535B2

    公开(公告)日:2022-05-03

    申请号:US16393310

    申请日:2019-04-24

    Abstract: In an optical detection system, received light can be concentrated and presented to a single-pixel photodetector (or an array of relatively few photodetectors). Concentration of received light can be performed by curved concentrator such as a continuously-curved or faceted reflector. A portion or an entirety of the detector might be blinded (e.g., desensitized) by bright interferers such as the sun. An electro-optic shutter such as a liquid crystal (LC) structure can be used to selectively transmit or mask-off portions of the received light. For example, an LC structure can have regions of selectable opacity for a specified polarization of incident light. The LC structure can be controlled to render certain region opaque, such as to suppress interference from unwanted interferers such as the sun, bright lights, or unwanted reflections. An LC structure can also be used to implement a scanned transmit/receive technique.

    Scaling fixed-point fast Fourier transforms in radar and sonar applications

    公开(公告)号:US09977116B2

    公开(公告)日:2018-05-22

    申请号:US14875281

    申请日:2015-10-05

    Inventor: Boris Lerner

    Abstract: Present disclosure describes an improved scaling mechanism for a multi-stage fixed-point FFT algorithm used to process signals received by radar or sonar systems. Proposed scaling includes scaling an output of every pair of consecutive butterfly stages of the FFT algorithm by a scaling factor equal to two times of the inverse of a growth factor for the pair of consecutive butterfly stages for the FFT algorithm for a purely complex exponential input signal. Besides this scaling, input signals are allowed to overflow by saturation. Such mechanism yields adequate performance of radar and sonar receivers implementing fixed-point FFTs for any types of input signals, from random to substantially complex exponential or sinusoidal signals. Proposed scaling achieves a balance between having signal to noise ratio (SNR) that is possible to obtain for a particular input signal and SNR that is needed to successfully process that signal for radar and sonar applications.

    Fixed-point high dynamic range fast fourier transforms

    公开(公告)号:US09946687B2

    公开(公告)日:2018-04-17

    申请号:US15008984

    申请日:2016-01-28

    Inventor: Boris Lerner

    CPC classification number: G06F17/142

    Abstract: A method for generating a Fast Fourier Transform (FFT) is disclosed. The method includes providing an input signal to two or more fixed-point FFT algorithms that apply different scaling to reduce growth of their output, resulting in each of the FFT algorithms yielding an array of FFT output values characterized by a different gain. The method further includes determining, on a per-FFT output value basis, whether an output value of an FFT algorithm with a relatively high gain was clipped due to saturation. If not, then the output value of that FFT algorithm is included in the final FFT. Otherwise, an output value of an FFT algorithm with a lower gain is included in the final FFT. Reconstructing the final FFT by such combination of values from different FFTs allows benefiting from the advantages of both higher- and lower-gain FFTs while avoiding or minimizing their disadvantages.

    FFT accelerator
    18.
    发明授权
    FFT accelerator 有权
    FFT加速器

    公开(公告)号:US09098449B2

    公开(公告)日:2015-08-04

    申请号:US13837055

    申请日:2013-03-15

    CPC classification number: G06F17/142

    Abstract: An FFT operation is performed by dividing n time-domain input points into a plurality of groups of m points, performing a plurality of constant-geometry butterfly operations on each of the groups of m points, and finally performing at least one in-place butterfly operation on the group of n points.

    Abstract translation: 通过将n个时域输入点划分成多个m个点进行FFT操作,对m个点的每个组执行多个恒定几何蝶形运算,并且最后执行至少一个就地蝴蝶 对n组进行操作。

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