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    PARALLEL ATOMIC INCREMENT
    2.
    发明申请
    PARALLEL ATOMIC INCREMENT 有权
    并行原子增量

    公开(公告)号：US20140344545A1

    公开(公告)日：2014-11-20

    申请号：US13896588

    申请日：2013-05-17

    Applicant: ANALOG DEVICES, INC.

    Inventor： Boris Lerner ,  John L. Redford

    IPC: G06F13/16

    CPC classification number: G06F13/1657 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/52 ,  G06F13/1663

    Abstract: Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of “hits” to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value.

    Abstract translation: 本公开的某些示例性实施例可以提供并行化的原子增量。 vgather指令将多个处理元素返回到存储器位置的值。 vgather_hit指令返回到存储器位置的“命中”数量的函数。 在一个实施例中，该功能是一致的。 在另一实施例中，该功能是具有小于或等于接收返回值的处理元件的顺序指定的命中数。

    MEMORY ARCHITECTURE
    3.
    发明申请
    MEMORY ARCHITECTURE 审中-公开
    内存架构

    公开(公告)号：US20140115278A1

    公开(公告)日：2014-04-24

    申请号：US14017301

    申请日：2013-09-03

    Applicant: ANALOG DEVICES, INC.

    Inventor： John L. Redford ,  Boris Lerner

    IPC: G06F12/00

    CPC classification number: G06F12/00 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3824 ,  G06F13/161 ,  G06F13/1631 ,  G06F13/1663

    Abstract: According to one example embodiment, an arbiter is disclosed to mediate memory access requests from a plurality of processing elements. If two or more processing elements try to access data within the same word in a single memory bank, the arbiter permits some or all of the processing elements to access the word. If two or more processing elements try to access different data words in the same memory bank, the lowest-ordered processing element is granted access and the others are stalled.

    Abstract translation: 根据一个示例实施例，公开了仲裁器来介入来自多个处理元件的存储器访问请求。 如果两个或多个处理元件尝试访问单个存储体中相同单词内的数据，则仲裁器允许部分或全部处理元件访问该单词。 如果两个或多个处理元件尝试访问同一存储体中的不同数据字，则最低有序处理元件被授予访问权限，而其他数据字被停止。

    SCALING FIXED-POINT FAST FOURIER TRANSFORMS IN RADAR AND SONAR APPLICATIONS
    5.
    发明申请
    SCALING FIXED-POINT FAST FOURIER TRANSFORMS IN RADAR AND SONAR APPLICATIONS 有权

    公开(公告)号：US20170097405A1

    公开(公告)日：2017-04-06

    申请号：US14875281

    申请日：2015-10-05

    Applicant: ANALOG DEVICES, INC.

    Inventor： Boris Lerner

    IPC: G01S7/35 ,  G01S15/58 ,  G01S15/42 ,  G01S13/58 ,  G01S13/42

    CPC classification number: G01S7/352 ,  G01S13/42 ,  G01S13/583 ,  G01S15/42 ,  G01S15/58 ,  G01S2007/356

    Abstract: Present disclosure describes an improved scaling mechanism for a multi-stage fixed-point FFT algorithm used to process signals received by radar or sonar systems. Proposed scaling includes scaling an output of every pair of consecutive butterfly stages of the FFT algorithm by a scaling factor equal to two times of the inverse of a growth factor for the pair of consecutive butterfly stages for the FFT algorithm for a purely complex exponential input signal. Besides this scaling, input signals are allowed to overflow by saturation. Such mechanism yields adequate performance of radar and sonar receivers implementing fixed-point FFTs for any types of input signals, from random to substantially complex exponential or sinusoidal signals. Proposed scaling achieves a balance between having signal to noise ratio (SNR) that is possible to obtain for a particular input signal and SNR that is needed to successfully process that signal for radar and sonar applications.

    Parallel atomic increment
    6.
    发明授权
    Parallel atomic increment 有权
    平行原子增量

    公开(公告)号：US09146885B2

    公开(公告)日：2015-09-29

    申请号：US13896588

    申请日：2013-05-17

    Applicant: ANALOG DEVICES, INC.

    Inventor： Boris Lerner ,  John L. Redford

    IPC: G06F12/00 ,  G06F13/16 ,  G06F9/52

    CPC classification number: G06F13/1657 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/52 ,  G06F13/1663

    Abstract: Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of “hits” to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value.

    Abstract translation: 本公开的某些示例性实施例可以提供并行化的原子增量。 vgather指令将多个处理元素返回到存储器位置的值。 vgather_hit指令返回到存储器位置的“命中”数量的函数。 在一个实施例中，该功能是一致的。 在另一个实施例中，该功能是具有小于或等于接收返回值的处理元件的顺序指定的命中数。

    THREAD OFFSET COUNTER
    8.
    发明申请
    THREAD OFFSET COUNTER 有权
    螺纹偏移计数器

    公开(公告)号：US20150154027A1

    公开(公告)日：2015-06-04

    申请号：US14096580

    申请日：2013-12-04

    Applicant: ANALOG DEVICES, INC.

    Inventor： Boris Lerner

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3867 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/325 ,  G06F9/3851

    Abstract: In an example, there is disclosed a digital signal processor having a register containing a modular integer configured for use as a thread offset counter. In a multi-stage, pipelined loop, which may be implemented in microcode, the main body of the loop has only one repeating stage. On each stage, the operation executed by each thread of the single repeating stage is identified by the sum of a fixed integer and the thread offset counter. After each pass through the loop, the thread offset counter is incremented, thus maintaining pipelined operation of the single repeating stage.

    Abstract translation: 在一个示例中，公开了一种数字信号处理器，其具有包含被配置为用作线偏移计数器的模数整数的寄存器。 在可以以微代码实现的多级流水线循环中，循环的主体仅具有一个重复阶段。 在每个阶段，由单个重复阶段的每个线程执行的操作由固定整数和线程偏移计数器的总和来标识。 每次通过循环后，螺纹偏移计数器递增，从而保持单个重复级的流水线操作。

    FFT ACCELERATOR
    9.
    发明申请
    FFT ACCELERATOR 有权
    FFT加速器

    公开(公告)号：US20140280421A1

    公开(公告)日：2014-09-18

    申请号：US13837055

    申请日：2013-03-15

    Applicant: ANALOG DEVICES, INC.

    Inventor： Ning Yang ,  David Miller ,  Boris Lerner ,  Guolin Pan ,  Steven L. Cox ,  Jiang Wu

    IPC: G06F17/14

    CPC classification number: G06F17/142

    Abstract: An FFT operation is performed by dividing n time-domain input points into a plurality of groups of m points, performing a plurality of constant-geometry butterfly operations on each of the groups of m points, and finally performing at least one in-place butterfly operation on the group of n points.

    Abstract translation: 通过将n个时域输入点划分成多个m个点进行FFT操作，对m个点的每个组执行多个恒定几何蝶形运算，并且最后执行至少一个就地蝴蝶 对n组进行操作。

    OPTICAL SYSTEM WITH SHUTTER AND CONCENTRATOR
    10.
    发明申请
    OPTICAL SYSTEM WITH SHUTTER AND CONCENTRATOR 审中-公开

    公开(公告)号：US20200341143A1

    公开(公告)日：2020-10-29

    申请号：US16393310

    申请日：2019-04-24

    Applicant: Analog Devices, Inc.

    Inventor： Harvey Weinberg ,  Boris Lerner

    IPC: G01S17/02 ,  G02B27/10 ,  H04N5/235 ,  G02B27/09

    Abstract: In an optical detection system, received light can be concentrated and presented to a single-pixel photodetector (or an array of relatively few photodetectors). Concentration of received light can be performed by curved concentrator such as a continuously-curved or faceted reflector. A portion or an entirety of the detector might be blinded (e.g., desensitized) by bright interferers such as the sun. An electro-optic shutter such as a liquid crystal (LC) structure can be used to selectively transmit or mask-off portions of the received light. For example, an LC structure can have regions of selectable opacity for a specified polarization of incident light. The LC structure can be controlled to render certain region opaque, such as to suppress interference from unwanted interferers such as the sun, bright lights, or unwanted reflections. An LC structure can also be used to implement a scanned transmit/receive technique.

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