公开(公告)号：US5731235A

公开(公告)日：1998-03-24

申请号：US739170

申请日：1996-10-30

申请人： Anand Srinivasan ,  Sujit Sharan ,  Gurtej S. Sandhu

发明人： Anand Srinivasan ,  Sujit Sharan ,  Gurtej S. Sandhu

IPC分类号： H01L21/02 ,  H01L21/318

CPC分类号： H01L28/40 ,  H01L21/3185

摘要： A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, the silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer. Also, a method of forming a capacitor dielectric layer over a capacitor plate layer includes, a) forming a first layer of dielectric material over a capacitor plate layer; b) conducting a pin-hole widening wet etch of the first layer; and c) after the wet etch, forming a pin-hole plugging second layer of dielectric material on the first layer and within the widened pin-holes.

摘要翻译： 一种形成氮化硅的方法包括：a）在衬底上形成包含氮化硅的第一层; b）在第一层上形成包含硅的第二层; 以及c）将所述第二层的硅氮化成氮化硅以形成包含氮化硅的层，所述氮化硅层包括所述第一层和所述第二层的氮化硅。 此外，形成氮化硅电容器电介质层的方法包括：a）形成第一电容器板层; b）在所述第一电容器板层上形成第一氮化硅层; c）在氮化硅层上形成硅层; d）将硅层氮化成第二氮化硅层; 以及e）在所述第二氮化硅层上方形成第二电容器板层。 此外，在电容器板层上形成电容器电介质层的方法包括：a）在电容器板层上形成介电材料的第一层; b）进行第一层的针孔加宽湿蚀刻; 以及c）在湿蚀刻之后，在第一层上和扩宽的针孔内形成针孔堵塞的第二介电材料层。

公开(公告)号：US06499425B1

公开(公告)日：2002-12-31

申请号：US09236277

申请日：1999-01-22

申请人： Gurtej S. Sandhu ,  Sujit Sharan ,  Anand Srinivasan

发明人： Gurtej S. Sandhu ,  Sujit Sharan ,  Anand Srinivasan

IPC分类号： C23C16509

CPC分类号： C23C16/45565 ,  C23C16/34 ,  C23C16/452 ,  C23C16/45514 ,  C23C16/45574 ,  H01J37/32357 ,  H01J37/3244

摘要： In a plasma processing apparatus, a showerhead is provided that allows for selective ionization of one or more process gasses within the showerhead. The showerhead allows the gasses to react after they exit the showerhead. As a result, a greater volume of materials are. available for deposition on a wafer surface during a chemical vapor deposition process than would be available in a process that remotely generates plasma. In addition, less damage is done to the wafer that would be done in a process that generates plasma next to the wafer.

摘要翻译： 在等离子体处理装置中，提供了一种喷头，其允许在喷头内选择性地电离一个或多个处理气体。 喷头允许气体在出口喷淋头后作出反应。 因此，更大量的材料是。 可以在化学气相沉积工艺期间沉积在晶片表面上，而不是在远程产生等离子体的工艺中可用。 此外，在晶片旁边产生等离子体的工艺中将对晶片造成较少的损坏。

公开(公告)号：US06952051B1

公开(公告)日：2005-10-04

申请号：US09627649

申请日：2000-07-28

申请人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

发明人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L21/76837

摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

摘要翻译： 层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面 材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。 具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工 。 公开了形成层间电介质结构的各种方法。

公开(公告)号：US07642204B2

公开(公告)日：2010-01-05

申请号：US10769430

申请日：2004-01-30

申请人： Anand Srinivasan ,  Gurtej Sandhu ,  Ravi Iyer

发明人： Anand Srinivasan ,  Gurtej Sandhu ,  Ravi Iyer

IPC分类号： H01L21/316

CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/31629

摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

摘要翻译： 一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。 另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。 另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

公开(公告)号：US06841463B1

公开(公告)日：2005-01-11

申请号：US09627381

申请日：2000-07-28

申请人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

发明人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L21/76837

摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

摘要翻译： 层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面 材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。 具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工 。 公开了形成层间电介质结构的各种方法。

公开(公告)号：US06727190B2

公开(公告)日：2004-04-27

申请号：US09146839

申请日：1998-09-03

申请人： Anand Srinivasan ,  Gurtej Sandhu ,  Ravi Iyer

发明人： Anand Srinivasan ,  Gurtej Sandhu ,  Ravi Iyer

IPC分类号： H01L21316

CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/31629

摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.

摘要翻译： 一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。 另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。 另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

公开(公告)号：US6107686A

公开(公告)日：2000-08-22

申请号：US249659

申请日：1999-02-12

申请人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

发明人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L21/76837

摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

摘要翻译： 层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面 材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。 具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工 。 公开了形成层间电介质结构的各种方法。

公开(公告)号：US6107183A

公开(公告)日：2000-08-22

申请号：US677514

申请日：1996-07-10

申请人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

发明人： Gurtej Sandhu ,  Anand Srinivasan ,  Ravi Iyer

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  H01L21/76837

摘要： An interlevel dielectric structure includes forming first and second dielectric layers between which are located lines of a conductive material that are also formed with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.

摘要翻译： 层间电介质结构包括形成第一和第二电介质层，它们之间位于导电材料的定位线之间，导电材料的导电材料线之间的空间中还形成介电材料，电介质材料的下表面延伸低于下部电介质材料 与其相邻的导电材料的线的表面，并且电介质材料的上表面比与其相邻的导电材料的上表面延伸，从而减少导电材料线之间的条纹和总电容。 具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工 。 公开了形成层间电介质结构的各种方法。

公开(公告)号：US20160215324A1

公开(公告)日：2016-07-28

申请号：US15023568

申请日：2014-09-23

申请人： Anand SRINIVASAN ,  Anand K. RAMASUBRAMANIAN ,  Jose L. LOPEZ-RIBOT ,  Christopher R. FREI

发明人： Anand Srinivasan ,  Anand K. Ramasubramanian ,  Jose L. Lopez-Ribot ,  Christopher R. Frei

IPC分类号： C12Q1/18

CPC分类号： C12Q1/18

摘要： The present disclosure provides for systems, devices, products, and methods for detecting and identifying microbial organisms in a sample as well as testing antimicrobial susceptibility of microbial organisms.

摘要翻译： 本公开提供用于检测和鉴定样品中微生物生物体的系统，装置，产品和方法以及测试微生物生物的抗微生物敏感性。

公开(公告)号：US09305057B2

公开(公告)日：2016-04-05

申请号：US12913636

申请日：2010-10-27

申请人： Alexandre de Castro Alves ,  Unmesh Deshmukh ,  Hoyong Park ,  Shailendra Mishra ,  Anand Srinivasan

发明人： Alexandre de Castro Alves ,  Unmesh Deshmukh ,  Hoyong Park ,  Shailendra Mishra ,  Anand Srinivasan

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/30516 ,  G06F17/30557

摘要： A framework or infrastructure (extensibility framework/infrastructure) for extending the indexing capabilities of an event processing system. The capabilities of an event processing system may be extended to support indexing schemes, including related data types and operations, which are not natively supported by the event processing system. The extensibility is enabled by one or more plug-in extension components called data cartridges.

摘要翻译： 用于扩展事件处理系统的索引功能的框架或基础设施（扩展框架/基础架构）。 可以扩展事件处理系统的能力，以支持索引方案，包括相关的数据类型和操作，这些事件处理系统本身不支持。 扩展性由一个或多个称为数据盒式的插件扩展组件启用。