公开(公告)号：US4947477A

公开(公告)日：1990-08-07

申请号：US164097

申请日：1988-03-04

申请人： Wendell L. Little

发明人： Wendell L. Little

IPC分类号： G06F12/06

CPC分类号： G06F12/0638

摘要： A central processing unit with partitionable program and data memory includes a CRT (10) which is interfaced with an embedded program/data memory (14). The embedded memory (14) is a random access memory which has a user-defined partition address that defines an address above which all addresses are associated with program memory and below which all addresses are associated with data memory. The partition address is stored in a memory control register (106) and can be loaded therein upon initialization of the CPU (10). When the program address or the data address exceeds the address in the embedded memory (14), the CPU (10) is allowed to access external program memory (24) and external data memory (26). This is controlled by an allocation/range control logic circuit (108).

摘要翻译： 具有可分割程序和数据存储器的中央处理单元包括与嵌入式程序/数据存储器（14）接口的CRT（10）。 嵌入式存储器（14）是具有用户定义的分区地址的随机存取存储器，其定义了一个地址，在该地址上，所有地址与程序存储器相关联，并且所有地址都与数据存储器相关联。 分区地址存储在存储器控制寄存器（106）中，并且可以在CPU（10）初始化时加载分配地址。 当程序地址或数据地址超过嵌入式存储器（14）中的地址时，CPU（10）被允许访问外部程序存储器（24）和外部数据存储器（26）。 这由分配/范围控制逻辑电路（108）控制。

公开(公告)号：US06691219B2

公开(公告)日：2004-02-10

申请号：US09924249

申请日：2001-08-07

申请人： Edward Tangkwai Ma ,  Frank V. Taylor, III ,  Stephen N. Grider ,  Wendell L. Little

发明人： Edward Tangkwai Ma ,  Frank V. Taylor, III ,  Stephen N. Grider ,  Wendell L. Little

IPC分类号： G06F1200

CPC分类号： G06F15/7814

摘要： The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.

摘要翻译： 本发明提供一种能够以三种地址模式之一支持扩展寻址能力的8位微控制器。 基于新地址控制（ACON）特殊功能寄存器（SFR）的设置，微控制器以传统的16位地址模式，24位分页地址模式或24位连续地址模式工作。 24位分页地址模式是符合标准16位地址范围的传统编译器的二进制代码，但允许通过新的地址页（AP）支持多达16M字节的程序存储器和16M字节的数据存储器， SFR，新的第一个扩展数据指针（DPX）SFR和一个新的第二个扩展数据指针（DPX1）寄存器。 24位连续模式需要一个24位地址编译器，通过向基本指令添加一个操作数和/或周期，支持整个24位地址范围内的连续程序流程。

公开(公告)号：US5754462A

公开(公告)日：1998-05-19

申请号：US283267

申请日：1988-12-09

申请人： Wendell L. Little

发明人： Wendell L. Little

IPC分类号： G06F1/24 ,  G06F1/30 ,  G06F1/32 ,  G06F11/00 ,  G06F11/14 ,  G06F13/00

CPC分类号： G06F11/0754 ,  G06F1/24 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3209 ,  G06F11/1415

摘要： A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. The microprocessor can access the auxilary chip to ascertain the power history. That is, the microprocessor can direct an interrupt to the auxilary chip, which will cause the auxiliary chip to respond with a signal which indicates to the microprocessor whether the power supply voltage is heading up or down. When the microprocessor is reset at power-up, the present invention permits the microprocessor to determine (by querying the auxiliary chip) whether the supply voltage is marginal, so that the microprocessor does not go into full operation until the supply voltage is high enough.

摘要翻译： 一种包括微处理器（或微控制器）和辅助芯片的系统，其监视系统电源电压并执行微处理器的相关功能。 微处理器可以访问辅助芯片以确定电源历史。 也就是说，微处理器可以将中断引导到辅助芯片，这将使辅助芯片响应于向微处理器指示电源电压是向上还是向下的信号。 当微处理器在上电时复位时，本发明允许微处理器确定（通过询问辅助芯片）电源电压是否是边缘的，使得微处理器在电源电压足够高之​​前不会进入全面工作。

公开(公告)号：US5590343A

公开(公告)日：1996-12-31

申请号：US504228

申请日：1995-07-19

申请人： Michael L. Bolan ,  Wendell L. Little

发明人： Michael L. Bolan ,  Wendell L. Little

IPC分类号： G06F1/24 ,  G06F1/30 ,  G06F1/32 ,  G06F11/00 ,  G06F11/14

CPC分类号： G06F11/0754 ,  G06F1/24 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3209 ,  G06F11/0757 ,  G06F11/1415

摘要： A system connects to an external contact pad that comprises a battery, a high-impedance load element powered by the battery and connected to pull a voltage potential of an external contact pad in a particular direction; a power supply connected to receive current from an AC line, the power supply carries a voltage; a switch connected to disconnect the power supply from the AC line; logic module connected to detect a voltage transition on the external contact pad caused when a user touches the external contact pad and to selectively operate the switch when the voltage transition is detected, the logic also connected to the battery and the power supply; and at least one microprocessor connected to be powered by the power supply.

摘要翻译： 系统连接到包括电池的外部接触焊盘，由电池供电并被连接以沿特定方向拉动外部接触焊盘的电压的高阻抗负载元件; 电源，连接以从AC线路接收电流，电源承载电压; 连接用于断开AC电源的电源的开关; 逻辑模块连接以检测当用户触摸外部接触焊盘时引起的外部接触焊盘上的电压转换，并且当检测到电压转换时选择性地操作开关，该逻辑还连接到电池和电源; 以及连接到由电源供电的至少一个微处理器。

公开(公告)号：US5249298A

公开(公告)日：1993-09-28

申请号：US998897

申请日：1992-12-28

申请人： Michael L. Bolan ,  Wendell L. Little

发明人： Michael L. Bolan ,  Wendell L. Little

IPC分类号： G06F1/24 ,  G06F1/30 ,  G06F1/32 ,  G06F11/00 ,  G06F11/14

CPC分类号： G06F11/0754 ,  G06F1/24 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3209 ,  G06F11/1415

摘要： A power-switching device (such as a gate-controlled TRIAC) is used to connect and disconnect a computer system's power supply unit from the power-line connection. This power-switching device is controlled by a battery-powered circuit. The battery-powered circuit monitors a contact pad, and powers up the system when the user touches the contact. Thus, when the system is powered down, all parts of the system are disconnected from AC power.

摘要翻译： 电源切换设备（如门控TRIAC）用于连接和断开计算机系统的电源单元与电源线连接。 该电源开关装置由电池供电的电路控制。 电池供电的电路监视触点板，并在用户触摸触点时上电系统。 因此，当系统断电时，系统的所有部件都与交流电源断开连接。

公开(公告)号：US5237699A

公开(公告)日：1993-08-17

申请号：US884269

申请日：1992-05-08

申请人： Wendell L. Little ,  Stephen N. Grider

发明人： Wendell L. Little ,  Stephen N. Grider

IPC分类号： G06F1/30

CPC分类号： G06F1/30

摘要： A battery-backed microprocessor which enters a known state on power-down. This is achieved, even if the microprocessor does not permit a single-cycle reset, by providing clock intercept circuitry on chip. When system power failure is detected, the clock intercept circuitry disconnects the external clock, activates a reset command, and then generates several clock cycles using an internal clock generator after the reset command. As many clock cycles are generated as is needed, with the particular architecture being used, to reach a predetermined state.

摘要翻译： 电池供电的微处理器，在掉电时进入已知状态。 这是通过在芯片上提供时钟截取电路来实现的，即使微处理器不允许单周期复位。 当检测到系统电源故障时，时钟截取电路断开外部时钟，激活复位命令，然后在复位命令后使用内部时钟发生器产生几个时钟周期。 随着所使用的特定架构的需要，生成许多时钟周期以达到预定状态。

公开(公告)号：US5203000A

公开(公告)日：1993-04-13

申请号：US617480

申请日：1990-11-15

申请人： Don Folkes ,  Wendell L. Little

发明人： Don Folkes ,  Wendell L. Little

IPC分类号： G06F1/24 ,  G06F1/30 ,  G06F1/32 ,  G06F11/00 ,  G06F11/14

CPC分类号： G06F11/0754 ,  G06F1/24 ,  G06F1/30 ,  G06F1/3203 ,  G06F1/3209 ,  G06F11/1415

摘要： A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. In one mode of operation (for use with a low-power CMOS processor), the auxiliary chip sends an interrupt to the microprocessor when the power supply falls to a first level, and also resets the microprocessor when the supply voltage reaches a second preset level on the way up (i.e. while power is being restored). In a selectable second mode of operation (for use with NMOS processor), the auxiliary chip resets the processor when the power supply is on the way down.

摘要翻译： 一种包括微处理器（或微控制器）和辅助芯片的系统，其监视系统电源电压并执行微处理器的相关功能。 在一种操作模式（用于低功耗CMOS处理器）中，辅助芯片在电源降至第一级时向微处理器发送一个中断，并且当电源电压达到第二预设电平时，复位微处理器 在路上（即电力恢复）。 在可选择的第二操作模式（用于NMOS处理器）中，当电源正在下降时，辅助芯片将复位处理器。

公开(公告)号：US4885716A

公开(公告)日：1989-12-05

申请号：US232403

申请日：1988-08-15

申请人： Wendell L. Little

发明人： Wendell L. Little

IPC分类号： G06F7/50 ,  G06F7/503

CPC分类号： G06F7/503 ,  G06F2207/3872

摘要： A carry chain includes a plurality of carry latches (20') which are disposed along a carry propagating line (12) to propagate a carry signal to a latch node (18). During precharge of the latch node (18), a precharge transistor (26') pulls the node to a logic one. During the precharge cycle, an N-channel transistor (34) which is a portion of the latch (20') is disconnected from the latch node (18) by a transistor (38). After the precharge cycle, this N-channel transistor (34) is reconnected to the latch node (18). This provides a low source impedance to quickly discharge the associated latch nodes (18) as the carry propagates along the carry chain (12).

摘要翻译： 进位链包括沿着进位传播线（12）设置以将进位信号传送到锁存节点（18）的多个进位锁存器（20'）。 在锁存节点（18）的预充电期间，预充电晶体管（26'）将节点拉到逻辑1。 在预充电循环期间，作为锁存器（20'）的一部分的N沟道晶体管（34）通过晶体管（38）与锁存节点（18）断开。 在预充电周期之后，该N沟道晶体管（34）被重新连接到锁存节点（18）。 这提供了低的源阻抗，以便随着进位沿着进位链（12）的传播而快速放电相关联的锁存节点（18）。

公开(公告)号：US4506167A

公开(公告)日：1985-03-19

申请号：US469541

申请日：1982-05-26

申请人： Wendell L. Little ,  Barry W. Herold

发明人： Wendell L. Little ,  Barry W. Herold

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K19/017 ,  H03K23/30

CPC分类号： H03K3/35625 ,  H03K3/037 ,  H03K3/356156

摘要： A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.

摘要翻译： 高速逻辑锁存电路由用于锁存逆变器的一对逆变器和反馈开关组成。 当禁止锁存时，一对输入切换装置允许数据进入锁存器。 该配置允许高速度，减少的基板面积和真正的互补输出。

公开(公告)号：US5978927A

公开(公告)日：1999-11-02

申请号：US611036

申请日：1996-03-05

申请人： Stephen M. Curry ,  Wendell L. Little ,  David A. Bunsey, Jr.

发明人： Stephen M. Curry ,  Wendell L. Little ,  David A. Bunsey, Jr.

IPC分类号： G06F13/42 ,  G06F1/04

CPC分类号： G06F13/4213

摘要： In a data bus environment where a host device and a plurality of other devices are connected to the bus, the time required for the first and the last device to respond to a host request is measured. Once the time required between the first and the last response is known, then a read/write window time can be minimized thereby increasing the speed of communication over the data bus.

摘要翻译： 在主机设备和多个其他设备连接到总线的数据总线环境中，测量第一和最后一个设备响应主机请求所需的时间。 一旦知道第一个和最后一个响应之间所需的时间，则可以使读/写窗口时间最小化，从而增加数据总线上的通信速度。