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1.发明授权公开(公告)号：US06691219B2
公开(公告)日：2004-02-10
申请号：US09924249
申请日：2001-08-07
IPC分类号： G06F1200
CPC分类号： G06F15/7814
摘要： The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.
摘要翻译： 本发明提供一种能够以三种地址模式之一支持扩展寻址能力的8位微控制器。 基于新地址控制（ACON）特殊功能寄存器（SFR）的设置，微控制器以传统的16位地址模式，24位分页地址模式或24位连续地址模式工作。 24位分页地址模式是符合标准16位地址范围的传统编译器的二进制代码，但允许通过新的地址页（AP）支持多达16M字节的程序存储器和16M字节的数据存储器， SFR，新的第一个扩展数据指针（DPX）SFR和一个新的第二个扩展数据指针（DPX1）寄存器。 24位连续模式需要一个24位地址编译器，通过向基本指令添加一个操作数和/或周期，支持整个24位地址范围内的连续程序流程。
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公开(公告)号：US06868505B2
公开(公告)日：2005-03-15
申请号：US09924239
申请日：2001-08-07
申请人： Edward Tang Kwai Ma , Stephen N. Grider , Frank V. Taylor, III , Joseph P. Gorski , Andrew D. Jones , Ann Little
发明人： Wendell L. Little
CPC分类号： G06F15/7814
摘要： Methods, systems, and arrangements enable efficient reprogramming of a memory block of a microcontroller. Two blocks of memory each have a different logical location with respect to a processor of the microcontroller. The first memory may store vector information to be executed by the processor. The second memory may store data information. The logical location of each memory block is dependent on the value of a pre-determined bit in a specified register. When a user wishes to reprogram the contents of the first memory, the user enters new code into the second memory. Upon completion, the value of the pre-determined bit is changed, and the logical locations of the first and second memories are interchanged. In effect, the newly entered code from the second memory is accessed as if it were in the first memory (e.g., from an addressing perspective), and the processor may execute the new program (e.g., after the processor undergoes a system reset).
摘要翻译： 方法，系统和布置使得能够对微控制器的存储块进行有效的重新编程。 两块存储器相对于微控制器的处理器具有不同的逻辑位置。 第一存储器可以存储要由处理器执行的矢量信息。 第二个存储器可以存储数据信息。 每个存储器块的逻辑位置取决于指定寄存器中预定位的值。 当用户希望重新编程第一存储器的内容时，用户将新的代码输入到第二存储器中。 一旦完成，改变预定位的值，并且互换第一和第二存储器的逻辑位置。 实际上，来自第二存储器的新输入的代码被访问，就好像它在第一存储器中（例如，从寻址的角度），并且处理器可以执行新程序（例如，在处理器经历系统复位之后）。
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3.发明授权
公开(公告)号：US06038655A
公开(公告)日：2000-03-14
申请号：US783718
申请日：1997-01-16
IPC分类号： G06F1/08 , H03K19/003 , G06F9/35
CPC分类号： G06F1/08 , H03K19/00361
摘要： A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.
摘要翻译： 微处理器板载RAM通过寻址和一个存储器单元的子集提供通常的随机存取，其内容在与数据总线并行的辅助总线上连续可用。 当RAM子集包含用于寄存器间接寻址的寄存器时，该辅助总线可用于寄存器间接寻址，而不需要单独的寄存器读取。 处理器还具有两级输出驱动器，用于限制最大输出电流和反馈控制的时钟周期分区。
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公开(公告)号：US5237699A
公开(公告)日：1993-08-17
申请号：US884269
申请日：1992-05-08
IPC分类号： G06F1/30
CPC分类号： G06F1/30
摘要： A battery-backed microprocessor which enters a known state on power-down. This is achieved, even if the microprocessor does not permit a single-cycle reset, by providing clock intercept circuitry on chip. When system power failure is detected, the clock intercept circuitry disconnects the external clock, activates a reset command, and then generates several clock cycles using an internal clock generator after the reset command. As many clock cycles are generated as is needed, with the particular architecture being used, to reach a predetermined state.
摘要翻译： 电池供电的微处理器，在掉电时进入已知状态。 这是通过在芯片上提供时钟截取电路来实现的，即使微处理器不允许单周期复位。 当检测到系统电源故障时，时钟截取电路断开外部时钟，激活复位命令，然后在复位命令后使用内部时钟发生器产生几个时钟周期。 随着所使用的特定架构的需要，生成许多时钟周期以达到预定状态。
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公开(公告)号：US5473271A
公开(公告)日：1995-12-05
申请号：US15691
申请日：1993-02-09
IPC分类号： G06F1/08 , H03K19/003 , H03K19/084
CPC分类号： G06F1/08 , H03K19/00361
摘要： A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.
摘要翻译： 微处理器板载RAM通过寻址和一个存储器单元的子集提供通常的随机存取，其内容在与数据总线并行的辅助总线上连续可用。 当RAM子集包含用于寄存器间接寻址的寄存器时，该辅助总线可用于寄存器间接寻址，而不需要单独的寄存器读取。 处理器还具有两级输出驱动器，用于限制最大输出电流和反馈控制的时钟周期分区。
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6.发明授权
公开(公告)号：US5212774A
公开(公告)日：1993-05-18
申请号：US282702
申请日：1988-12-09
CPC分类号： G06F11/2294 , G06F8/65 , H04L29/06 , H04M11/00 , G06F11/20 , G06F11/3656
摘要： Preferred embodiments include systems with two processors and an interconnected modem, one processor functioning as a control for both the modem and the second processor. This permits remote communication with the second processor for test or reconfiguration purposes.
摘要翻译： 优选实施例包括具有两个处理器和互连调制解调器的系统，一个处理器用作调制解调器和第二处理器的控制器。 这允许与第二处理器的远程通信用于测试或重新配置目的。
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公开(公告)号：US5515540A
公开(公告)日：1996-05-07
申请号：US174584
申请日：1993-12-28
CPC分类号： G06F21/75 , G06F2221/2143
摘要： A nonvolatile microcontroller (or microprocessor) with improved security against tampering, including attempts at active intrusion. According to this invention, a battery-backed microcontroller includes encryption and power management functions, and is combined with a battery and a volatile semiconductor memory (e.g. an SRAM). The microcontroller supplies power to the semiconductor memory (either from a system power supply or from the battery). When a security violation is detected, the microcontroller wipes its encryption registers, and also grounds the power-output pin to the memory. This will destroy all data in the volatile memory.
摘要翻译： 一种具有改进的防篡改安全性的非易失性微控制器（或微处理器），包括主动入侵的尝试。 根据本发明，电池支持的微控制器包括加密和电源管理功能，并且与电池和易失性半导体存储器（例如，SRAM）组合。 微控制器为半导体存储器供电（从系统电源或从电池供电）。 当检测到安全违规时，微控制器擦除其加密寄存器，并将电源输出引脚接地到存储器。 这将破坏易失性存储器中的所有数据。
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公开(公告)号：US5381540A
公开(公告)日：1995-01-10
申请号：US985513
申请日：1992-12-02
CPC分类号： G06F13/26
摘要： Interrupt circuitry for a processor comprises a plurality of interrupt inputs, an interrupt output, combinatorial logic with a plurality of combinatorial logic inputs connected to the plurality of interrupt inputs and with a combinatorial logic output connected to the interrupt output wherein an interrupt output signal at the interrupt output is a function of interrupt signals at the plurality of interrupt inputs; and an interrupt mode select connected to the combinatorial logic wherein an interrupt mode select signal from the interrupt mode select controls the function. The interrupt mode select signal from the interrupt mode select selects the function to be either AND or OR. The circuitry also comprises a mask register having a plurality of mask register inputs and a plurality of mask register outputs, the plurality of mask register inputs connected to the plurality of interrupt inputs and the plurality of mask register outputs connected to the plurality of combinatorial logic inputs wherein a mask register bit pattern in the mask register conditions a corresponding subset (possibly empty) of the interrupt signals at the plurality of interrupt inputs to make the function and the interrupt output signal at the interrupt output not depend upon the corresponding subset.
摘要翻译： 用于处理器的中断电路包括多个中断输入，中断输出，组合逻辑，多个组合逻辑输入连接到多个中断输入，以及连接到中断输出的组合逻辑输出，其中中断输出信号 中断输出是多个中断输入端的中断信号的函数; 以及连接到组合逻辑的中断模式选择，其中来自中断模式选择的中断模式选择信号控制该功能。 来自中断模式的中断模式选择信号选择将该功能选择为或或。 电路还包括具有多个屏蔽寄存器输入和多个屏蔽寄存器输出的屏蔽寄存器，多个屏蔽寄存器输入连接到多个中断输入以及连接到多个组合逻辑输入的多个屏蔽寄存器输出 其中掩模寄存器中的掩码寄存器位模式对多个中断输入端的中断信号的对应子集（可能是空的）进行调整，以使中断输出处的功能和中断输出信号不依赖于对应的子集。
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9.发明授权
公开(公告)号：US4908790A
公开(公告)日：1990-03-13
申请号：US166383
申请日：1988-03-10
IPC分类号： G06F1/30
CPC分类号： G06F1/30 , Y10T307/625
摘要： Backup battery switching circuitry for a microcomputer or a microprocessor includes circuitry for selectively coupling a backup battery to a power supply output terminal of the microcomputer or microprocessor for powering an external circuit such as a static RAM. The backup battery voltage is normally coupled to the power supply output terminal in the absence of a primary power source, but may be isolated from the power supply output terminal when a predetermined voltage is applied to a logic input pin and a predetermined sequence of events is executed by the microcomputer or microprocessor.
摘要翻译： 用于微型计算机或微处理器的备用电池切换电路包括用于将备用电池选择性地耦合到微计算机或微处理器的电源输出端子以供外部电路（例如静态RAM）供电的电路。 在没有主电源的情况下，备用电池电压通常耦合到电源输出端子，但是当预定电压被施加到逻辑输入引脚时，可以与电源输出端子隔离，并且预定的事件序列是 由微机或微处理器执行。
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公开(公告)号：US06996725B2
公开(公告)日：2006-02-07
申请号：US09932247
申请日：2001-08-16
发明人： Wendell L. Little
IPC分类号： G06F1/24
摘要： Methods, systems, and arrangements enable increased security for a processor, including by implementing block encryption. The block may include multiple instructions and/or operations to be executed by the processor. The block may also include multiple bytes that are read into the processor byte by byte. Once a block-wide encrypted buffer has been filled from an external memory source, the block may be decrypted using an encryption algorithm (e.g., the Data Encryption Standard (DES), the triple DES, etc.), and the decrypted block may be forwarded to a decrypted buffer. The decrypted block may thereafter be moved into a cache, which may optionally be organized into an equivalent block width (e.g., for each way of a multi-way cache). Therefore, when a processing core/instruction decoder needs a new instruction, it may retrieve one from the cache, directly from the decrypted buffer, or from external memory (e.g., after undergoing decryption).
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