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59 条记录 (耗时 0.024 秒)

    Post-silicon control of phase locked loop charge pump current
    11.
    发明授权
    Post-silicon control of phase locked loop charge pump current 有权
    锁相环电荷泵电流后硅控制

    公开(公告)号：US06664828B2

    公开(公告)日：2003-12-16

    申请号：US10131306

    申请日：2002-04-24

    申请人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

    发明人： Claude Gauthier ,  Brian Amick ,  Pradeep Trivedi ,  Dean Liu

    IPC分类号： H03L706

    CPC分类号： H03L7/0898 ,  H03L7/0896 ,  H03L7/18

    摘要： A post-silicon technique for adjusting a current of a charge pump in a phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the charge pump, where the adjustment circuit is controllable to facilitate an internal biasing of the charge pump. Such control of the charge pump current in a phase locked loop allows a designer to achieve desired PLL performance characteristics after the PLL has been fabricated.

    摘要翻译： 提供了一种用于调节锁相环中的电荷泵电流的后硅技术。 该技术涉及使用可操作地连接到电荷泵的调节电路，其中调节电路是可控制的，以便于电荷泵的内部偏置。 锁相环中的电荷泵电流的这种控制允许设计者在PLL被制造之后实现期望的PLL性能特性。

    Using a push/pull buffer to improve delay locked loop performance
    12.
    发明授权
    Using a push/pull buffer to improve delay locked loop performance 有权
    使用推/拉缓冲来改善延迟锁定环的性能

    公开(公告)号：US06650157B2

    公开(公告)日：2003-11-18

    申请号：US10044103

    申请日：2002-01-11

    申请人： Brian Amick ,  Claude Gauthier ,  Dean Liu

    发明人： Brian Amick ,  Claude Gauthier ,  Dean Liu

    IPC分类号： H03L706

    CPC分类号： H03L7/0814 ,  H03L7/07

    摘要： A delay locked loop that uses a differential push/pull buffer is provided. The differential push/pull buffer of the DLL is used to create a buffered output that closely follows the characteristics of the buffer's input over a range of temperature, power supply noise operating conditions, and process (manufacturing) variations. Further, an integrated circuit that contains a delay locked loop that uses a differential push/pull buffer is provided. Further, a delay locked loop with means for buffering a delayed signal is provided. Further, a method for buffering a delayed clock signal using a differential push/pull buffer is provided.

    摘要翻译： 提供了使用差分推/拉缓冲器的延迟锁定环。 DLL的差分推/拉缓冲器用于创建缓冲输出，该缓冲输出在温度范围，电源噪声运行条件和过程（制造）变化等方面与缓冲器输入的特性密切相关。 此外，提供了包含使用差分推/拉缓冲器的延迟锁定环路的集成电路。 此外，提供了一种用于缓冲延迟信号的装置的延迟锁定环。 此外，提供了一种使用差分推/拉缓冲器来缓存延迟时钟信号的方法。

    Jitter estimation for a phase locked loop
    13.
    发明授权
    Jitter estimation for a phase locked loop 有权
    锁相环的抖动估计

    公开(公告)号：US06819192B2

    公开(公告)日：2004-11-16

    申请号：US10075750

    申请日：2002-02-14

    申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： H03B100

    CPC分类号： G01R29/26 ,  G06F17/5036 ,  H03L7/18

    摘要： A method for estimating jitter in a phase locked loop is provided. The estimation is determined from a simulation that uses a representative power supply waveform having noise as an input. Further, a computer system for estimating jitter in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to estimate jitter in a phase locked loop is provided.

    摘要翻译： 提供了一种用于估计锁相环中的抖动的方法。 从使用具有噪声的代表性电源波形作为输入的仿真确定估计。 此外，提供了一种用于估计锁相环中的抖动的计算机系统。 此外，提供了其上记录有适于估计锁相环中的抖动的指令的计算机可读介质。

    Method for simulating power supply noise in an on-chip temperature sensor
    15.
    发明授权
    Method for simulating power supply noise in an on-chip temperature sensor 有权
    模拟片上温度传感器电源噪声的方法

    公开(公告)号：US06748339B2

    公开(公告)日：2004-06-08

    申请号：US10075206

    申请日：2002-02-14

    申请人： Brian Amick ,  Claude Gauthier ,  Dean Liu ,  Pradeep Trivedi

    发明人： Brian Amick ,  Claude Gauthier ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： G06F1500

    CPC分类号： G06F17/5036

    摘要： A method for estimating accuracy of an on-chip temperature sensor is provided. A representative power supply waveform having noise is input into a simulation of the on-chip temperature sensor and the accuracy of the on-chip temperature sensor is estimated from the simulation. A computer system for estimating accuracy of an on-chip temperature sensor is also provided. A computer-readable medium having instructions adapted to input a representative power supply waveform having noise into a simulation of an on-chip temperature sensor and estimate accuracy of the on-chip temperature sensor from the simulation is provided.

    摘要翻译： 提供了一种用于估计片上温度传感器的精度的方法。 将具有噪声的代表性电源波形输入到片上温度传感器的模拟中，并且从仿真估计片上温度传感器的精度。 还提供了一种用于估计片上温度传感器的精度的计算机系统。 提供了一种具有适于将具有噪声的代表性电源波形输入到片上温度传感器的模拟并且从模拟估计片上温度传感器的精度的指令的计算机可读介质。

    Optimization of loop bandwidth for a phase locked loop
    16.
    发明授权
    Optimization of loop bandwidth for a phase locked loop 有权
    锁相环的环路带宽优化

    公开(公告)号：US06671863B2

    公开(公告)日：2003-12-30

    申请号：US10075339

    申请日：2002-02-14

    申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： G06F945

    CPC分类号： G06F17/5036

    摘要： A method for optimizing loop bandwidth in a phase locked loop is provided. A representative power supply waveform having noise is input into a simulation of the phase locked loop; an estimate of jitter is determined; and the loop bandwidth of the phase looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a phase locked loop is provided.

    摘要翻译： 提供了一种优化锁相环路环路带宽的方法。 具有噪声的代表性电源波形被输入到锁相环的仿真中; 确定抖动的估计; 并且调整相位循环的循环带宽，直到抖动低于预选值。 此外，提供了一种用于优化锁相环中的环路带宽的计算机系统。 此外，提供了一种其上记录有适于优化锁相环中的环路带宽的指令的计算机可读介质。

    Chip/package resonance damping using controlled package series resistance
    17.
    发明授权
    Chip/package resonance damping using controlled package series resistance 有权
    芯片/封装谐振阻尼采用受控封装串联电阻

    公开(公告)号：US06822345B2

    公开(公告)日：2004-11-23

    申请号：US10118840

    申请日：2002-04-09

    申请人： Claude Gauthier ,  Brian Amick

    发明人： Claude Gauthier ,  Brian Amick

    IPC分类号： H02J700

    CPC分类号： H01L23/5286 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T307/615 ,  H01L2924/00

    摘要： A method and apparatus for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least one resistive element connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path.

    摘要翻译： 提供一种用于降低集成电路的电源路径的阻抗的方法和装置。 电源路径包括第一电源线和向集成电路提供电力的第二电源线。 连接在第一电源线和第二电源线之间的至少一个电阻元件被调节以减小电源路径的阻抗。

    Phase locked loop input receiver design with delay matching feature
    18.
    发明授权
    Phase locked loop input receiver design with delay matching feature 有权
    锁相环输入接收机设计具有延迟匹配功能

    公开(公告)号：US06778027B2

    公开(公告)日：2004-08-17

    申请号：US10121806

    申请日：2002-04-12

    申请人： Claude Gauthier ,  Pradeep Trivedi ,  Brian Amick

    发明人： Claude Gauthier ,  Pradeep Trivedi ,  Brian Amick

    IPC分类号： H03L700

    CPC分类号： G06F1/10 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/18

    摘要： A phase locked loop that includes a receiver circuit for matching delays of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver circuit employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry control the generation of substantially delay matched system and feedback clocks.

    摘要翻译： 提供了一种锁相环，其包括用于在系统时钟的延迟和在锁相环的输入处的反馈时钟的匹配的接收器电路。 接收器电路采用系统时钟路径电路来输入系统时钟和反馈时钟路径电路以输入反馈时钟，其中与系统时钟路径电路相关联的电流和负载电阻以及与反馈时钟路径电路相关联的电流和负载电阻 控制生成基本上延迟匹配的系统和反馈时钟。

    Digital delay locked loop with extended phase capture range
    19.
    发明授权
    Digital delay locked loop with extended phase capture range 有权
    具延时相位捕捉范围的数字延迟锁定环

    公开(公告)号：US07107475B1

    公开(公告)日：2006-09-12

    申请号：US10690302

    申请日：2003-10-21

    申请人： Brian Amick ,  Dong Joon Yoon ,  Tri Tran ,  Gajendra Singh ,  Aparna Ramachandran ,  Claude Gauthier

    发明人： Brian Amick ,  Dong Joon Yoon ,  Tri Tran ,  Gajendra Singh ,  Aparna Ramachandran ,  Claude Gauthier

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12 ,  H03K2005/00241 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/10

    摘要： A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updated to indicate whether the delay array needs to provide more delay or less delay. The digital delay locked loop also uses a detection circuit that monitors for a predetermined condition of the delay code. In response to detection of the predetermined condition, the delay code is automatically reset to a value different than a value of the delay code present at a previous reset or initial startup of the digital delay locked loop.

    摘要翻译： 数字延迟锁定环使用延迟阵列将输入信号延迟由延迟码指示的量。 将所得到的延迟信号的相位与输入信号的相应相位进行比较，并且根据比较，更新延迟码以指示延迟阵列是否需要提供更多的延迟或更小的延迟。 数字延迟锁定环路还使用监视延迟码的预定条件的检测电路。 响应于预定条件的检测，延迟码被自动复位到与数字延迟锁定环的先前复位或初始启动时存在的延迟码的值不同的值。

    Adjustable capacitances for DLL loop and power supply noise filters
    20.
    发明授权
    Adjustable capacitances for DLL loop and power supply noise filters 有权
    DLL环路和电源噪声滤波器的可调电容

    公开(公告)号：US06614275B1

    公开(公告)日：2003-09-02

    申请号：US10116316

    申请日：2002-04-04

    申请人： Brian Amick ,  Claude Gauthier

    发明人： Brian Amick ,  Claude Gauthier

    IPC分类号： H03K706

    CPC分类号： H03L7/093 ,  H03K5/133 ,  H03K2005/00032 ,  H03L7/0812

    摘要： A delay locked loop having an adjustable capacitance stage is provided. The adjustable capacitance stage facilitates a selective post-silicon adjustment of capacitance amounts between a DLL loop filter capacitance and a power supply noise filter capacitance, thereby allowing a designer to reduce capacitance area space wastage and to obtain an optimal DLL performance level.

    摘要翻译： 提供具有可调电容级的延迟锁定环。 可调电容级有助于在DLL环路滤波器电容和电源噪声滤波器电容之间的电容量的选择性后硅调整，从而允许设计者减少电容面积空间浪费并获得最佳DLL性能水平。