公开(公告)号：US08138050B2

公开(公告)日：2012-03-20

申请号：US12555879

申请日：2009-09-09

申请人： Vassilios Papageorgiou ,  Jan Hoentschel ,  Robert Mulfinger ,  Casey Scott

发明人： Vassilios Papageorgiou ,  Jan Hoentschel ,  Robert Mulfinger ,  Casey Scott

IPC分类号： H01L21/336

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.

摘要翻译： 可以基于漏极和源极区域中的不对称形成的空腔来调节晶体管特性，以便保持应变诱发机制，同时提供获得漏极和源极区域的不对称构造的可能性，同时避免高度复杂的注入 过程。 为此，在相应的腔蚀刻工艺中的去除速率可以基于倾斜的离子注入工艺被不对称地修饰。

公开(公告)号：US20100081244A1

公开(公告)日：2010-04-01

申请号：US12555879

申请日：2009-09-09

申请人： Vassilios Papageorgiou ,  Jan Hoentschel ,  Robert Mulfinger ,  Casey Scott

发明人： Vassilios Papageorgiou ,  Jan Hoentschel ,  Robert Mulfinger ,  Casey Scott

IPC分类号： H01L21/336

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.

摘要翻译： 可以基于漏极和源极区域中的不对称形成的空腔来调节晶体管特性，以便保持应变诱发机制，同时提供获得漏极和源极区域的不对称构造的可能性，同时避免高度复杂的注入 过程。 为此，在相应的腔蚀刻工艺中的去除速率可以基于倾斜的离子注入工艺被不对称地修饰。

公开(公告)号：US08466520B2

公开(公告)日：2013-06-18

申请号：US13470441

申请日：2012-05-14

申请人： Stephan Kronholz ,  Vassilios Papageorgiou ,  Gunda Beernink

发明人： Stephan Kronholz ,  Vassilios Papageorgiou ,  Gunda Beernink

IPC分类号： H01L21/02

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

摘要： In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.

摘要翻译： 在晶体管中，诸如硅/锗，硅/碳等的应变诱导半导体合金可以通过提供逐渐形成的空腔而非常接近沟道区域，然后可以用应变诱导半导体合金 。 为此，可以使用不同蚀刻行为的两个或更多个“一次性”间隔元件，以便在相应空腔的不同深度处限定不同的横向偏移。 因此，即使对于复杂的半导体器件，也可以实现增强的均匀性，从而降低晶体管的变化性。

公开(公告)号：US20100193882A1

公开(公告)日：2010-08-05

申请号：US12688999

申请日：2010-01-18

申请人： Jan Hoentschel ,  Vassilios Papageorgiou ,  Uwe Griebenow

发明人： Jan Hoentschel ,  Vassilios Papageorgiou ,  Uwe Griebenow

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： The dopant profile of a transistor may be obtained on the basis of an in situ doped strain-inducing semiconductor alloy wherein a graded dopant concentration may be established along the height direction. Consequently, the semiconductor alloy may be positioned in close proximity to the channel region, thereby enhancing the overall strain-inducing efficiency, while not unduly compromising the finally obtained dopant profile. Furthermore, additional implant species may be incorporated prior to selectively growing the semiconductor alloy, thereby avoiding implantation-induced relaxation of the internal strain.

摘要翻译： 可以基于原位掺杂的应变诱导半导体合金获得晶体管的掺杂物分布，其中可以沿着高度方向建立梯度掺杂剂浓度。 因此，可以将半导体合金定位在靠近沟道区的位置，从而提高整体的应变诱导效率，同时不会过度损害最终获得的掺杂剂分布。 此外，可以在选择性地生长半导体合金之前引入额外的植入物种，从而避免植入诱导的内部应变松弛。

公开(公告)号：US20100134167A1

公开(公告)日：2010-06-03

申请号：US12604532

申请日：2009-10-23

申请人： Vassilios Papageorgiou ,  Maciej Wiatr ,  Jan Hoentschel

发明人： Vassilios Papageorgiou ,  Maciej Wiatr ,  Jan Hoentschel

IPC分类号： H03K5/04

CPC分类号： G06F11/008

摘要： The device degradation of integrated circuits may be compensated for by appropriately adapting the duty cycle of the clock signal. For this purpose, a correlation between the duty cycle and the overall performance characteristics of the integrated circuit may be established and may be used during the normal field operation of the device in order to modify the duty cycle. Hence, an efficient control strategy may be implemented since the duty cycle may be efficiently controlled, while at the same time a change of clock signal frequency and/or an increase of supply voltage may not be required.

摘要翻译： 可以通过适当调整时钟信号的占空比来补偿集成电路的器件劣化。 为此，可以建立集成电路的占空比和整体性能特性之间的相关性，并且可以在设备的正常现场操作期间使用以改变占空比。 因此，可以实现有效的控制策略，因为可以有效地控制占空比，同时可能不需要时钟信号频率的改变和/或电源电压的增加。

公开(公告)号：US07616021B2

公开(公告)日：2009-11-10

申请号：US11624258

申请日：2007-01-18

申请人： Vassilios Papageorgiou ,  Amado Ramirez ,  Michael Zhouying Su

发明人： Vassilios Papageorgiou ,  Amado Ramirez ,  Michael Zhouying Su

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/287 ,  G01R31/3025

摘要： An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path coupling a second node of the degradable test structure and the second external interface pin. Another integrated circuit device includes a non-volatile memory device, a counter comprising an input configured to receive a first clock signal and an output to provide a count value, and control logic configured to store the count value of the counter in the non-volatile memory, whereby the non-volatile memory is externally accessible.

摘要翻译： 集成电路装置包括可降解测试结构，第一外部接口引脚和第二外部接口引脚，耦合可降解测试结构的第一节点和第一外部接口引脚的第一导电路径，以及耦合第二外部接口引脚的第二导电路径 可降解测试结构的节点和第二个外部接口引脚。 另一个集成电路装置包括非易失性存储装置，计数器，包括被配置为接收第一时钟信号的输入和输出以提供计数值，以及控制逻辑，被配置为将计数器的计数值存储在非易失性存储装置中 存储器，由此非易失性存储器可从外部访问。

公开(公告)号：US20120223363A1

公开(公告)日：2012-09-06

申请号：US13470441

申请日：2012-05-14

申请人： Stephan Kronholz ,  Vassilios Papageorgiou ,  Gunda Beernink

发明人： Stephan Kronholz ,  Vassilios Papageorgiou ,  Gunda Beernink

IPC分类号： H01L29/78

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

摘要： In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.

摘要翻译： 在晶体管中，诸如硅/锗，硅/碳等的应变诱导半导体合金可以通过提供逐渐形成的空腔而非常接近沟道区域，然后可以用应变诱导半导体合金 。 为此，可以使用不同蚀刻行为的两个或更多个“一次性”间隔元件，以便在相应空腔的不同深度处限定不同的横向偏移。 因此，即使对于复杂的半导体器件，也可以实现增强的均匀性，从而降低晶体管的变化性。

公开(公告)号：US08202777B2

公开(公告)日：2012-06-19

申请号：US12640765

申请日：2009-12-17

申请人： Stephan Kronholz ,  Vassilios Papageorgiou ,  Gunda Beernink

发明人： Stephan Kronholz ,  Vassilios Papageorgiou ,  Gunda Beernink

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

摘要： In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices.

摘要翻译： 在晶体管中，诸如硅/锗，硅/碳等的应变诱导半导体合金可以通过提供逐渐形成的空腔而非常接近沟道区域，然后可以用应变诱导半导体合金 。 为此，可以使用不同蚀刻行为的两个或更多个“一次性”间隔元件，以便在相应空腔的不同深度处限定不同的横向偏移。 因此，即使对于复杂的半导体器件，也可以实现增强的均匀性，从而降低晶体管的变化性。

公开(公告)号：US08154084B2

公开(公告)日：2012-04-10

申请号：US12473726

申请日：2009-05-28

申请人： Jan Hoentschel ,  Vassilios Papageorgiou ,  Belinda Hannon

发明人： Jan Hoentschel ,  Vassilios Papageorgiou ,  Belinda Hannon

IPC分类号： H01L21/70

CPC分类号： H01L27/092 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

摘要翻译： 可以在适当的制造方案的基础上，以不同导电类型的晶体管提供硅/锗材料和硅/碳材料，而不会不利地导致整个工艺的复杂性。 此外，在形成相应的应变半导体合金之前，可以通过空腔的暴露的表面区域提供适当的注入物质，从而另外有助于提高总体晶体管性能。 在其它实施例中，硅/碳材料可以形成在P沟道晶体管和N沟道晶体管中，而相应的拉伸应变分量可以通过在P沟道晶体管中的应力存储技术过度补偿。 因此，可以将诸如增强P沟道晶体管的整体掺杂物分布的碳物质的有益效果与有效的应变分量组合，同时可以实现增强的整体工艺均匀性。

公开(公告)号：US20080174329A1

公开(公告)日：2008-07-24

申请号：US11624258

申请日：2007-01-18

申请人： Vassilios Papageorgiou ,  Amado Ramirez ,  Michael Zhuoying Su

发明人： Vassilios Papageorgiou ,  Amado Ramirez ,  Michael Zhuoying Su

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  G01R31/287 ,  G01R31/3025

摘要： An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path coupling a second node of the degradable test structure and the second external interface pin. Another integrated circuit device includes a non-volatile memory device, a counter comprising an input configured to receive a first clock signal and an output to provide a count value, and control logic configured to store the count value of the counter in the non-volatile memory, whereby the non-volatile memory is externally accessible.

摘要翻译： 集成电路装置包括可降解测试结构，第一外部接口引脚和第二外部接口引脚，耦合可降解测试结构的第一节点和第一外部接口引脚的第一导电路径，以及耦合第二外部接口引脚的第二导电路径 可降解测试结构的节点和第二个外部接口引脚。 另一集成电路装置包括非易失性存储装置，计数器，包括被配置为接收第一时钟信号的输入和输出以提供计数值，以及控制逻辑，被配置为将计数器的计数值存储在非易失性存储器装置中 存储器，由此非易失性存储器可从外部访问。