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公开(公告)号：US20220036630A1
公开(公告)日：2022-02-03
申请号：US17103382
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Jonathan M. Redshaw
Abstract: Disclosed techniques relate to forming single-instruction multiple-data (SIMD) groups during ray intersection traversal. In particular, ray intersection circuitry may include dedicated circuitry configured to traverse an acceleration data structure, but may dynamically form a SIMD group to transform ray coordinates when traversing from one level of the data structure to another. This may allow shader processors to execute the SIMD group to perform the transformation. Disclosed techniques may facilitate instancing of graphics models within the acceleration data structure.
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公开(公告)号：US20180137670A1
公开(公告)日：2018-05-17
申请号：US15870081
申请日：2018-01-12
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Justin A. Hensley
CPC classification number: G06T15/04 , G06T15/005 , G06T15/06 , G06T2210/36
Abstract: Techniques are disclosed relating to texture sampling operations. In some embodiments, multi-fetch sampling instructions specify a region of a texture in which multiple samples are to be performed and texture processing circuitry is configured to sample the texture multiple times within the region. In some embodiments, the locations of the samples are determined according to a formula, which may be pseudo-random. In some embodiments, the locations of the samples are jittered to produce stochastic results. In some embodiments, the locations of the samples are determined based on one or more stored sets of samples that have particular properties (e.g., blue noise, in some embodiments). In various embodiments, disclosed techniques may facilitate Monte Carlo sampling.
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公开(公告)号：US20170228919A1
公开(公告)日：2017-08-10
申请号：US15018252
申请日：2016-02-08
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Justin A. Hensley
CPC classification number: G06T15/04 , G06T15/005 , G06T15/06 , G06T2210/36
Abstract: Techniques are disclosed relating to texture sampling operations. In some embodiments, multi-fetch sampling instructions specify a region of a texture in which multiple samples are to be performed and texture processing circuitry is configured to sample the texture multiple times within the region. In some embodiments, the locations of the samples are determined according to a formula, which may be pseudo-random. In some embodiments, the locations of the samples are jittered to produce stochastic results. In some embodiments, the locations of the samples are determined based on one or more stored sets of samples that have particular properties (e.g., blue noise, in some embodiments). In various embodiments, disclosed techniques may facilitate Monte Carlo sampling.
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公开(公告)号：US09530237B2
公开(公告)日：2016-12-27
申请号：US14677280
申请日：2015-04-02
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Andrew Pomianowski , Anthony P. DeLaurier
CPC classification number: G06T15/04 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/80 , G06T2200/04 , G06T2200/12
Abstract: Techniques are disclosed relating to interpolation for texture mapping. In some embodiments, a graphics unit includes circuitry configured to map a texture to a screen space such that a set of multiple in the screen space falls between first and second adjacent texels of the texture in a first dimension. In some embodiments, the graphics unit also includes texture processing circuitry configured to perform different types of interpolation for pixels in the group of pixels. In these embodiments, this includes determining pixel attributes for first and second end groups of pixels in the set of pixels using a nearest-neighbor interpolation technique and attributes of the first and second texels respectively. In these embodiments, this also includes determining pixel attributes for an intermediate group of pixels in the set of pixels using a second, different interpolation technique and attributes of both the first and second texels.
Abstract translation: 公开了关于纹理映射的插值的技术。 在一些实施例中，图形单元包括被配置为将纹理映射到屏幕空间的电路，使得屏幕空间中的多个集合在第一维度中落在纹理的第一和第二相邻纹素之间。 在一些实施例中，图形单元还包括纹理处理电路，其被配置为对像素组中的像素执行不同类型的内插。 在这些实施例中，这包括使用最近邻内插技术和第一和第二纹素的属性来确定像素集合中的像素的第一和第二端组的像素属性。 在这些实施例中，这还包括使用第二不同的插值技术和第一和第二纹素两者的属性来确定像素集合中的中间像素组的像素属性。
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公开(公告)号：US11734871B2
公开(公告)日：2023-08-22
申请号：US17456483
申请日：2021-11-24
Applicant: Apple Inc.
Inventor： Christopher A. Burns
IPC: G06T15/06
CPC classification number: G06T15/06 , G06T2215/12
Abstract: Techniques are disclosed relating to primitive intersection testing for ray tracing in graphics processors. In some embodiments, a graphics processor includes ray intersection circuitry configured to perform an intersection test, which includes to: quantize a first representation of the primitive to generate a reduced-precision interval representation of the primitive, quantize a first representation of the ray to generate a reduced-precision interval representation of the ray, and determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray. The initial intersection result may be a conservative result such that a miss indicated by the initial intersection result is guaranteed not to be a hit for the first representation of the primitive and first representation of the ray. Disclosed techniques may improve performance, reduce power consumption, or both, relative to traditional techniques.
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Patent Agency Ranking
公开(公告)号：US11676327B2
公开(公告)日：2023-06-13
申请号：US17205680
申请日：2021-03-18
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Ali Rabbani Rankouhi , Justin A. Hensley , Richard W. Schreyer
IPC: G06T15/06 , G06F16/901 , G06T15/00
CPC classification number: G06T15/06 , G06F16/9027 , G06T15/005
Abstract: Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.
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公开(公告)号：US11645084B2
公开(公告)日：2023-05-09
申请号：US17470682
申请日：2021-09-09
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Liang-Kai Wang , Robert D. Kenney , Terence M. Potter
CPC classification number: G06F9/3887 , G06F9/30098 , G06T1/20 , G06T1/60
Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.
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公开(公告)号：US20220301254A1
公开(公告)日：2022-09-22
申请号：US17205680
申请日：2021-03-18
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Ali Rabbani Rankouhi , Justin A. Hensley , Richard W. Schreyer
IPC: G06T15/06 , G06T15/00 , G06F16/901
Abstract: Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.
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公开(公告)号：US20220036637A1
公开(公告)日：2022-02-03
申请号：US17103317
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
Abstract: Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.
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公开(公告)号：US20170293470A1
公开(公告)日：2017-10-12
申请号：US15092401
申请日：2016-04-06
Applicant: Apple Inc.
Inventor： Liang-Kai Wang , Terence M. Potter , Andrew M. Havlir , Yu Sun , Nicolas X. Pena , Xiao-Long Wu , Christopher A. Burns
IPC: G06F7/483
CPC classification number: G06F7/483 , G06F7/5443
Abstract: Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.
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