Display gate drivers with dynamic and reduced voltage swing

    公开(公告)号:US10923022B2

    公开(公告)日:2021-02-16

    申请号:US16692933

    申请日:2019-11-22

    Applicant: Apple Inc.

    Abstract: A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit in the chain of row driver circuits may include a master driver stage, a slave driver stage, and associated control circuitry configured to receive a clock signal and a pulse signal from a preceding row driver in the chain. The master driver stage may be biased using fixed nominal power supply voltages, whereas the slave driver stage may be biased using dynamically adjustable power supply voltages that are optionally reduced relative to that of the nominal power supply voltages. One or more of the master and slave driver stages may be a bootstrapping driver stage having a bootstrapping capacitor.

    Display gate drivers for generating low-frequency inverted pulses

    公开(公告)号:US11488538B1

    公开(公告)日:2022-11-01

    申请号:US17213041

    申请日:2021-03-25

    Applicant: Apple Inc.

    Abstract: A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit may include a scan driver circuit and a scan inverter circuit. An enable transistor may be interposed between the scan driver circuit and the scan inverter circuit and may be selectively disabled to decouple the scan inverter circuit from the scan driver circuit to allow the scan inverter circuit to operate independent from the scan driver circuit. The scan inverter circuit may include a transistor that receives a scan pulse signal from the scan driver circuit and may further include additional transistors connected in a negative feedback configuration to reduce a drain-to-source voltage across the transistor to reduce leakage across the transistor during blanking times.

    High Frame Rate Display
    17.
    发明申请

    公开(公告)号:US20190228726A1

    公开(公告)日:2019-07-25

    申请号:US16369319

    申请日:2019-03-29

    Applicant: Apple Inc.

    Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

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