公开(公告)号：US10319068B2

公开(公告)日：2019-06-11

申请号：US15587063

申请日：2017-05-04

Applicant: Apple Inc.

Inventor： Michael J. Swift ,  Michael Imbrogno ,  Gokhan Avkarogullari

IPC: G06T1/00 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00

Abstract: One disclosed embodiment includes memory allocation methods for use by a graphics processing unit in rendering graphics data for display. The method includes receiving a buffer attachment associated with a first rendering pass. The hardware prerequisites for operation of the first rendering pass is determined. The method also includes receiving an indication to not allocate system memory for the received buffer attachment. Thereafter, it may be determined whether the received buffer attachment will be loaded from or stored to by the subsequent rendering passes. If it is determined that the buffer attachment will be accessed by the subsequent rendering passes, an error message may be generated indicating that system memory must be allocated. If it is determined that the buffer attachment will not be accessed by the subsequent rendering passes, the buffer attachment is rendered without allocating system memory.

公开(公告)号：US20180181489A1

公开(公告)日：2018-06-28

申请号：US15389047

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Anthony P. DeLaurier ,  Owen C. Anderson ,  Michael J. Swift ,  Aaftab A. Munshi ,  Terence M. Potter

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F2212/455 ,  G06F2212/621 ,  G06T1/60

Abstract: Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.

公开(公告)号：US20170358054A1

公开(公告)日：2017-12-14

申请号：US15467268

申请日：2017-03-23

Applicant: Apple Inc.

Inventor： Bartosz Ciechanowski ,  Michael Imbrogno ,  Gokhan Avkarogullari ,  Nathaniel C. Begeman ,  Sean M. Gies ,  Michael J. Swift

IPC: G06T1/60 ,  G06T15/00 ,  G06T1/20

Abstract: One disclosed embodiment is directed to graphics processing method for displaying a user interface. The method includes executing a plurality of graphic processing operation in a single rendering pass. The rendering pass includes several render targets. At least one of the render targets is designated as a memory-less render target. The memory-less render target is used to store intermediate data. The intermediate data is combined with the outcome of at least one other graphics processing operation to generate a combined result. The combined result is stored in the frame buffer memory for display.