公开(公告)号：US11462608B2

公开(公告)日：2022-10-04

申请号：US17143939

申请日：2021-01-07

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Jiun-Jye Chang ,  Jung Yen Huang ,  Pei-En Chang ,  Rungrot Kitsomboonloha ,  Szu-Hsien Lee

IPC: G09G3/3225 ,  G09G3/3266 ,  H01L27/32 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49

Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.

公开(公告)号：US10354607B2

公开(公告)日：2019-07-16

申请号：US15684109

申请日：2017-08-23

Applicant: Apple Inc.

Inventor： Kwang Soon Park ,  Pei-En Chang ,  Szu-Hsien Lee

IPC: G09G3/36 ,  G09G3/3233

Abstract: A display may have an array of pixels. Rows of pixels may receive gate line signals over gate lines. Display driver circuitry may have an adjustable clock generator that generates a series of clock pulses with different respective fall times to help equalize kickback voltages in the pixels of different rows. Within each row, gate lines may be provided with multiple parallel lines shorted at a series of tap points to help equalize kickback voltages across the pixels of different columns. A clock path may be formed between the clock generator and gate driver circuits. The clock path may run along an edge of the array of pixels. To help equalize kickback voltages in the pixels of different rows, the clock path may have first and second parallel metal lines that are selectively shorted to each other at a series of tap point locations along the clock path.

公开(公告)号：US20230084423A1

公开(公告)日：2023-03-16

申请号：US17853649

申请日：2022-06-29

Applicant: Apple Inc.

Inventor： Myungjoon Choi ,  Jie Won Ryu ,  Hyunwoo Nho ,  Xiaokai Li ,  Kaikai Guo ,  Szu-Hsien Lee ,  Rungrot Kitsomboonloha ,  Pei-En Chang ,  Amit Nayyar ,  Vehbi Calayir

IPC: G09G3/20 ,  G06F3/041

Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.

公开(公告)号：US11605330B1

公开(公告)日：2023-03-14

申请号：US17853649

申请日：2022-06-29

Applicant: Apple Inc.

Inventor： Myungjoon Choi ,  Jie Won Ryu ,  Hyunwoo Nho ,  Xiaokai Li ,  Kaikai Guo ,  Szu-Hsien Lee ,  Rungrot Kitsomboonloha ,  Pei-En Chang ,  Amit Nayyar ,  Vehbi Calayir

IPC: G09G3/20 ,  G06F3/041

Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.

公开(公告)号：US11580905B2

公开(公告)日：2023-02-14

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US20210305353A1

公开(公告)日：2021-09-30

申请号：US17143939

申请日：2021-01-07

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Jiun-Jye Chang ,  Jung Yen Huang ,  Pei-En Chang ,  Rungrot Kitsomboonloha ,  Szu-Hsien Lee

IPC: H01L27/32 ,  G09G3/3266 ,  G09G3/3225

Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.

公开(公告)号：US10303013B2

公开(公告)日：2019-05-28

申请号：US15967441

申请日：2018-04-30

Applicant: Apple Inc.

Inventor： Hossein Nemati ,  Pei-En Chang ,  Yuan Chen ,  Tae Woon Cha ,  Sung H. Kim ,  Chia Hsuan Tai

IPC: G02F1/1343 ,  G02F1/1335 ,  H01L27/12 ,  G02F1/1345 ,  G02F1/1362 ,  G06F1/16 ,  G02F1/167

Abstract: An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The antialiasing pixels may include single-opening pixels that each have a single opaque masking layer opening and may include dual-opening pixels that each include a pair of opaque masking layer openings. The single-opening pixels may be stronger than the dual-opening pixels.

公开(公告)号：US20180308445A1

公开(公告)日：2018-10-25

申请号：US15684109

申请日：2017-08-23

Applicant: Apple Inc.

Inventor： Kwang Soon Park ,  Pei-En Chang ,  Szu-Hsien Lee

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3233 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/02

Abstract: A display may have an array of pixels. Rows of pixels may receive gate line signals over gate lines. Display driver circuitry may have an adjustable clock generator that generates a series of clock pulses with different respective fall times to help equalize kickback voltages in the pixels of different rows. Within each row, gate lines may be provided with multiple parallel lines shorted at a series of tap points to help equalize kickback voltages across the pixels of different columns. A clock path may be formed between the clock generator and gate driver circuits. The clock path may run along an edge of the array of pixels. To help equalize kickback voltages in the pixels of different rows, the clock path may have first and second parallel metal lines that are selectively shorted to each other at a series of tap point locations along the clock path.