公开(公告)号：US09384820B1

公开(公告)日：2016-07-05

申请号：US14738119

申请日：2015-06-12

Applicant: Apple Inc.

Inventor： Neeraj Parik ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1636 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4096 ,  G11C2211/4061

Abstract: A method and apparatus for aligning calibration segments for increased availability of a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto via a number of independently operable channels (interfaces). The memory controller may convey on each of the channels at least one corresponding data strobe signal. The data strobe signal in each channel may be periodically calibrated. The memory controller may be configured to align the periodic calibrations in time so that they are performed concurrently instead of in a staggered manner. During the time the calibrations are performed on each channel, the memory may be unavailable for normal accesses.

Abstract translation: 公开了一种用于对准校准段以提高存储器子系统的可用性的方法和装置。 在一个实施例中，存储器子系统包括存储器和经由多个可独立操作的通道（接口）耦合到其上的存储器控​​制器。 存储器控制器可以在每个通道上传送至少一个对应的数据选通信号。 可以周期地校准每个通道中的数据选通信号。 存储器控制器可以被配置为在时间上对准周期性校准，使得它们同时执行而不是以交错方式执行。 在每个通道执行校准时，存储器可能无法正常访问。

公开(公告)号：US20240061617A1

公开(公告)日：2024-02-22

申请号：US18497883

申请日：2023-10-30

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F13/1605 ,  G06F3/0644 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

公开(公告)号：US20220357879A1

公开(公告)日：2022-11-10

申请号：US17313811

申请日：2021-05-06

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

IPC: G06F3/06 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

公开(公告)号：US11221798B2

公开(公告)日：2022-01-11

申请号：US16751975

申请日：2020-01-24

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller is configured to transition between read turns and writes turn according to a turn schedule. In some embodiments, the memory controller also receives reports from circuitry requesting memory transactions and determines a current latency tolerance value based on the reports. In some embodiments, the memory controller is configured to switch from a write turn to a read turn prior to a scheduled switch based on the current latency tolerance meeting a threshold value.

公开(公告)号：US20200266810A1

公开(公告)日：2020-08-20

申请号：US16277263

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Yanzhe Liu

IPC: H03K5/156 ,  H03K3/017 ,  G11C11/409

Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.

公开(公告)号：US20150206558A1

公开(公告)日：2015-07-23

申请号：US14158404

申请日：2014-01-17

Applicant: Apple Inc.

Inventor： Bin Ni ,  Kai Lun Charles Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F12/1036 ,  G11C11/408 ,  G11C11/409

Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.

Abstract translation: 公开了用于监控和控制对动态随机存取存储器（DRAM）行的重复访问的系统和方法。 用于监测和控制对DRAM的重复访问的方法可以包括将DRAM的一组划分成多个逻辑块，将存储体的每一行映射到逻辑块之一，监视对逻辑块的访问，以及控制对 基于监控的逻辑块。