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    Calibration of clock signal for data transmission
    1.
    发明授权
    Calibration of clock signal for data transmission 有权
    校准数据传输的时钟信号

    公开(公告)号：US09477259B2

    公开(公告)日：2016-10-25

    申请号：US14597321

    申请日：2015-01-15

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Neeraj Parik ,  Sukalpa Biswas

    IPC: H04L7/00 ,  G06F1/12 ,  G06F1/00 ,  G06F1/08

    CPC classification number: G06F1/12 ,  G06F1/08

    Abstract: A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.

    Abstract translation: 公开了一种用于校准数据传输中使用的时钟信号的方法和装置。 该方法包括具有粗和细晶粒程序的校准。 粗粒度程序从当前眼睛的中心开始，并且在递减提供给时钟信号的延迟时执行读取，直到至少一个位失败。 这从眼睛的中心重复，直到再次至少一个位失败。 记录上下通过点。 细粒度过程包括从最下一个通过点向下递减执行读取，每个位失败的记录点直到全部失败。 细粒度过程还包括从上一个最后通过点增加每个位故障直到失败的记录点。 此后，基于校准数据确定与新眼睛的中心相对应的时钟延迟。

    SYSTEM FOR MANAGING MEMORY DEVICES
    2.
    发明申请
    SYSTEM FOR MANAGING MEMORY DEVICES 审中-公开

    公开(公告)号：US20180032281A1

    公开(公告)日：2018-02-01

    申请号：US15225343

    申请日：2016-08-01

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Peter F. Holland ,  Erik P. Machnicki ,  Robert E. Jeter ,  Rakesh L. Notani ,  Neeraj Parik ,  Marc A. Schaub

    IPC: G06F3/06 ,  G11C11/406

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

    Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

    Real-time resource handling in resource retry queue
    3.
    发明授权
    Real-time resource handling in resource retry queue 有权

    公开(公告)号：US10417146B1

    公开(公告)日：2019-09-17

    申请号：US15980713

    申请日：2018-05-15

    Applicant: Apple Inc.

    Inventor： Sridhar Kotha ,  Neeraj Parik ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Xiaoming Wang

    IPC: G06F13/16 ,  G06F12/0871 ,  G06F9/50

    Abstract: An embodiment of an apparatus includes a retry queue circuit, a transaction arbiter circuit, and a plurality of transaction buffers. The retry queue circuit may store one or more entries corresponding to one or more memory transactions. A position in the retry queue circuit of an entry of the one or more entries may correspond to a priority for processing a memory transaction corresponding to the entry. The transaction arbiter circuit may receive a real-time memory transaction from a particular transaction buffer. In response to a determination that the real-time memory transaction is unable to be processed, the transaction arbiter circuit may create an entry for the real-time memory transaction in the retry queue circuit. In response to a determination that a bulk memory transaction is scheduled for processing prior to the real-time memory transaction, the transaction arbiter circuit may upgrade the bulk memory transaction to use real-time memory resources.

    Memory interface system
    4.
    发明授权
    Memory interface system 有权

    公开(公告)号：US09697145B2

    公开(公告)日：2017-07-04

    申请号：US14738265

    申请日：2015-06-12

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Neeraj Parik

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F13/16 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02

    CPC classification number: G06F13/161 ,  G06F12/023 ,  G06F12/0646 ,  G06F2212/1044 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

    Abstract: In some embodiments, a memory interface system includes a memory interface circuit and a memory controller. The memory interface circuit is configured to communicate with a memory device. The memory controller is configured, in response to the memory device operating at a first frequency, to store configuration information corresponding to the memory device operating at a second frequency. The memory controller is further configured, in response to the memory device transitioning to the second frequency, to send the configuration information to the memory interface circuit. In some embodiments, storing the configuration information may result in some memory requests being provided to the memory device more quickly, as compared to a different memory interface system where the configuration information is not stored at the memory controller. Additionally, in some embodiments, storing the configuration information may result in the configuration information being transmitted to the memory interface circuit more efficiently.

    ESTABLISHING DEPENDENCY IN A RESOURCE RETRY QUEUE
    5.
    发明申请
    ESTABLISHING DEPENDENCY IN A RESOURCE RETRY QUEUE 审中-公开

    公开(公告)号：US20200050548A1

    公开(公告)日：2020-02-13

    申请号：US16102542

    申请日：2018-08-13

    Applicant: Apple Inc.

    Inventor： Sridhar Kotha ,  Neeraj Parik

    IPC: G06F12/0815 ,  G06F12/0804

    Abstract: A memory cache controller includes a transaction arbiter circuit and a retry queue circuit. The transaction arbiter circuit may determine whether a received memory transaction can currently be processed by a transaction pipeline. The retry queue circuit may queue memory transactions that the transaction arbiter circuit determines cannot be processed by the transaction pipeline. In response to receiving a memory transaction that is a cache management transaction, the retry queue circuit may establish a dependency from the cache management transaction to a previously stored memory transaction in response to a determination that both the previously stored memory transaction and the cache management transaction target a common address. Based on the dependency, the retry queue circuit may initiate a retry, by the transaction pipeline, of one or more of the queued memory transactions in the retry queue circuit

    REFERENCE VOLTAGE CALIBRATION USING A QUALIFIED WEIGHTED AVERAGE
    9.
    发明申请
    REFERENCE VOLTAGE CALIBRATION USING A QUALIFIED WEIGHTED AVERAGE 有权
    参考电压校准使用合格的加权平均值

    公开(公告)号：US20160292094A1

    公开(公告)日：2016-10-06

    申请号：US14676174

    申请日：2015-04-01

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Brijesh Tripathi ,  Kiran Kattel ,  Rakesh L. Notani ,  Fabien S. Faure ,  Sukalpa Biswas ,  Kai Lun Hsiung ,  Neeraj Parik ,  Venkata Ramana Malladi ,  Shiva Kumar ,  Chaitanya Polapragada ,  Allen Kim

    IPC: G06F13/16

    CPC classification number: G06F13/1668 ,  G06F13/1689 ,  Y02D10/14

    Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

    Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许在通信链路上执行周期性校准操作。 控制器可以基于初始值来确定与通信链路一起使用的参考电压的多个可能值。 可以使用每个可能的值执行校准操作，并且基于在校准操作期间测量的数据眼睛的宽度来评估操作的结果。 然后，控制器可以根据多个可能值中的每一个的分数从多个可能值中选择参考电压的新值。

    Calibration of Clock Signal for Data Transmission
    10.
    发明申请
    Calibration of Clock Signal for Data Transmission 有权
    用于数据传输的时钟信号校准

    公开(公告)号：US20160209866A1

    公开(公告)日：2016-07-21

    申请号：US14597321

    申请日：2015-01-15

    Applicant: Apple Inc.

    Inventor： Robert E. Jeter ,  Neeraj Parik ,  Sukalpa Biswas

    IPC: G06F1/12 ,  G06F1/08

    CPC classification number: G06F1/12 ,  G06F1/08

    Abstract: A method and apparatus for calibration of a clock signal used in data transmission is disclosed. The method includes a calibration having coarse and fine grain procedures. The coarse grain procedure begins from the center of a current eye and performs reads while decrementing the delay provided to the clock signal until at least one bit fails. This is repeated, from the center of the eye, incrementing until again at least one bit fails. The lower and upper last passing points are recorded. A fine grain procedure includes performing reads while decrementing, from the lower last passing point, recording points at which each bit fails until all fail. The fine grain procedure further includes incrementing, from the upper last passing point, recording points at which each bit fails until fail. Thereafter, a clock delay corresponding to the center of the new eye is determined based on the calibration data.

    Abstract translation: 公开了一种用于校准数据传输中使用的时钟信号的方法和装置。 该方法包括具有粗和细晶粒程序的校准。 粗粒度程序从当前眼睛的中心开始，并且在递减提供给时钟信号的延迟时执行读取，直到至少一个位失败。 这从眼睛的中心重复，直到再次至少一个位失败。 记录上下通过点。 细粒度过程包括从最下一个通过点向下递减执行读取，每个位失败的记录点直到全部失败。 细粒度过程还包括从上一个最后通过点增加每个位故障直到失败的记录点。 此后，基于校准数据确定与新眼睛的中心相对应的时钟延迟。

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