公开(公告)号：US20210271606A1

公开(公告)日：2021-09-02

申请号：US16804128

申请日：2020-02-28

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Yoong Chert Foo ,  Terence M. Potter ,  Frank W. Liljeros ,  Ralph C. Taylor

IPC: G06F12/1018 ,  G06F12/084

Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

公开(公告)号：US20230419585A1

公开(公告)日：2023-12-28

申请号：US17808392

申请日：2022-06-23

Applicant: Apple Inc.

Inventor： Adam J. Smith ,  Sergio V. Tota ,  Christopher G. Martin ,  Yoong Chert Foo ,  Terence M. Potter ,  Max J. Batley

IPC: G06T15/00 ,  G06F9/38

CPC classification number: G06T15/005 ,  G06F9/3887

Abstract: Techniques are disclosed relating to processor communications fabrics. In some embodiments, a processor includes multiple client circuitry and fabric circuitry that includes at least first and second instances of a tile. The tile may include: client inputs configured to interface with client circuits, tile inputs configured to interface with one or more other tile instances, and communication resources assignable to the client inputs and tile inputs. The communications resources may include: multiple internal links, client outputs configured to interface with client circuits, and tile outputs configured to interface with one or more other tile instances. Control circuitry may, in a given cycle, assign communication resources of a given tile instance to at least a portion of the client inputs and tile inputs for a next cycle, based on priority information. The control circuitry may update priority information based on assignment results over multiple cycles.

公开(公告)号：US11829298B2

公开(公告)日：2023-11-28

申请号：US16804128

申请日：2020-02-28

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Yoong Chert Foo ,  Terence M. Potter ,  Frank W. Liljeros ,  Ralph C. Taylor

IPC: G06F12/1018 ,  G06F12/084 ,  G06F30/392

CPC classification number: G06F12/1018 ,  G06F12/084 ,  G06F30/392 ,  G06F2212/622 ,  G06F2212/651

Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

公开(公告)号：US20220148249A1

公开(公告)日：2022-05-12

申请号：US17103462

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Yoong Chert Foo ,  Ali Rabbani Rankouhi ,  Justin A. Hensley ,  Jonathan M. Redshaw

IPC: G06T15/00 ,  G06F9/50 ,  G06F9/38 ,  G06T1/60

Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.