公开(公告)号：US20210159158A1

公开(公告)日：2021-05-27

申请号：US16698680

申请日：2019-11-27

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20240021582A1

公开(公告)日：2024-01-18

申请号：US18360749

申请日：2023-07-27

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/522 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H05K1/144 ,  H01L23/5226 ,  H01L23/49586 ,  H01L25/50

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

公开(公告)号：US20220375787A1

公开(公告)日：2022-11-24

申请号：US17323381

申请日：2021-05-18

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Kurtis LESCHKIES ,  Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Tapash CHAKRABORTY ,  Han-Wen CHEN ,  Steven VERHAVERBEKE

IPC: H01L21/768 ,  H01L21/48

Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.

公开(公告)号：US20220171281A1

公开(公告)日：2022-06-02

申请号：US17673951

申请日：2022-02-17

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Han-Wen CHEN ,  Chintan BUCH ,  Steven VERHAVERBEKE ,  Vincent DICAPRIO

IPC: G03F7/00 ,  H01L21/768 ,  G03F7/20

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.

公开(公告)号：US20220139884A1

公开(公告)日：2022-05-05

申请号：US17578271

申请日：2022-01-18

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/522 ,  H01L23/495 ,  H01L25/00

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

公开(公告)号：US20210159160A1

公开(公告)日：2021-05-27

申请号：US16886704

申请日：2020-05-28

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO ,  Bernhard STONAS ,  Jean DELMAS

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20200243432A1

公开(公告)日：2020-07-30

申请号：US16256809

申请日：2019-01-24

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Kyuil CHO ,  Prayudi LIANTO ,  Guan Huei SEE ,  Vincent DICAPRIO

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: A method for producing an electrical component is disclosed using a molybdenum adhesion layer, connecting a polyimide substrate to a copper seed layer and copper plated attachment.

公开(公告)号：US20200159113A1

公开(公告)日：2020-05-21

申请号：US16192546

申请日：2018-11-15

Applicant: Applied Materials, Inc.

Inventor： Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Han-Wen CHEN ,  Chintan BUCH ,  Steven VERHAVERBEKE ,  Vincent DICAPRIO

IPC: G03F7/00 ,  G03F7/20 ,  H01L21/768

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 μm.

公开(公告)号：US20190139788A1

公开(公告)日：2019-05-09

申请号：US16171000

申请日：2018-10-25

Applicant: Applied Materials, Inc.

Inventor： Boyi FU ,  Han-Wen CHEN ,  Kyuil CHO ,  Sivapackia GANAPATHIAPPAN ,  Roman GOUK ,  Steven VERHAVERBEKE ,  Nag B. PATIBANDLA ,  Yan ZHAO ,  Hou T. NG ,  Ankit VORA ,  Daihua ZHANG

IPC: H01L21/56 ,  H01L21/67

Abstract: Aspects of the disclosure generally relate to methods of immobilizing die on a substrate. In one method one or more immobilization features are formed in a selected pattern on a substrate. A die is positioned in contact with the one or more immobilization features and the substrate. The one or more immobilization features are cured, and a mold layer is formed on top of the cured one or more immobilization features and the die so as to encapsulate the die.