Abstract:
Semiconductor packages and methods for metallization of non-conducting surfaces for fabricating semiconductor packages are provided. In an embodiment, the method includes depositing an adhesion layer on a polymeric surface by an electroless deposition process. The polymeric surface defines a sidewall of a through-hole via and the adhesion layer comprises a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer by an immersion plating process. The copper seed layer displaces a portion of the adhesion layer. The method further includes filling the through-hole via with a copper containing layer.
Abstract:
In one implementation, a method of depositing a material on a substrate is provided. The method comprises positioning an aluminum-containing substrate in an electroplating solution, the electroplating solution comprising a non-aqueous solvent and a deposition precursor. The method further comprises depositing a coating on the aluminum-containing substrate, the coating comprising aluminum or aluminum oxide. Depositing the coating comprises applying a first current for a first time-period to nucleate a surface of the aluminum-containing substrate and applying a second current for a second time-period, wherein the first current is greater than the second current and the first time-period is less than the second time-period to form the coating on the nucleated surface of the aluminum-containing substrate.
Abstract:
Methods for selective dielectric deposition using self-assembled monolayer (SAM) are provided herein. A method of selectively depositing a low-k dielectric layer atop a substrate having an exposed silicon surface and an exposed silicon-containing surface, includes: (a) growing an organosilane based self-assembled monolayer atop the exposed silicon-containing surface, wherein the organosilane based self-assembled monolayer is thermally stable at a first temperature of greater than about 300 degrees Celsius; and (b) selectively depositing a low-k dielectric layer atop the exposed silicon surface of the substrate, wherein the organosilane based self-assembled monolayer inhibits deposition of the low-k dielectric layer atop the silicon-containing surface.
Abstract:
A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a grain orientation normal to a horizontal surface of the structure.
Abstract:
The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.
Abstract:
Single source precursors, methods to synthesize single source precursors and methods to deposit nanowire based thin films using single source precursors for high efficiency thermoelectric devices are provided herein. In some embodiments, a method of forming a single source precursor includes mixing a first compound with one of SbX3, SbX5, Sb2(SO4)3 or with one of BiX3, Bi(NO3)3, Bi(OTf)3, Bi(PO4), Bi(OAc)3, wherein the first compound is one of a lithium selenolate, a lithium tellurolate, a monoselenide, or a monotelluride.