公开(公告)号：US20230002268A1

公开(公告)日：2023-01-05

申请号：US17836162

申请日：2022-06-09

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Mahendran CHIDAMBARAM ,  Kangkang WANG ,  Ludovic GODET ,  Visweswaren SIVARAMAKRISHNAN

IPC: C03B33/02 ,  B23K26/0622 ,  B23K26/55

Abstract: A method and apparatus for substrate dicing are described. The method includes utilizing a laser to dice a substrate along a dicing path to form a perforated line around each device within the substrate. The dicing path is created by exposing the substrate to bursts of laser pulses at different locations around each device. The laser pulses are delivered to the substrate and may have a pulse repetition frequency of greater than about 25 MHz, a pulse width of less than about 15 picoseconds, and a laser wavelength of about 1.0 μm to about 5 μm.

公开(公告)号：US20220020590A1

公开(公告)日：2022-01-20

申请号：US16928252

申请日：2020-07-14

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Kurtis LESCHKIES ,  Roman GOUK ,  Steven VERHAVERBEKE ,  Visweswaren SIVARAMAKRISHNAN

IPC: H01L21/268 ,  H01L21/768 ,  H01L21/67 ,  H01L21/68 ,  B23K26/00 ,  B23K26/386

Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.

公开(公告)号：US20160035577A1

公开(公告)日：2016-02-04

申请号：US14775651

申请日：2014-03-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng LEI ,  Mohammad Kamruzzaman CHOWDHURY ,  Todd EGAN ,  Brad EATON ,  Madhava Rao YALAMANCHILI ,  Ajay KUMAR

IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/687 ,  B23K26/402 ,  H01L21/67 ,  H01L21/673 ,  H01L21/82 ,  B23K26/364

CPC classification number: H01L21/3086 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/67069 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67383 ,  H01L21/68707 ,  H01L21/78 ,  H01L21/82

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.

Abstract translation: 具有多个IC的切割基板的方法。 一种方法包括形成多层掩模，该多层掩模包括设置在半导体衬底上的水溶性基底层上的激光能量吸收不可光限定的顶涂层。 因为激光吸收材料层是不可光定型的，所以可以避免与常规光致抗蚀剂配方相关的材料成本。 掩模是用激光划线工艺直接写入图案，以提供具有间隙的图案化掩模。 图案化使IC之间的衬底的区域暴露。 激光发射带（例如，UV带和/或绿色带）内的掩模层的吸收促进了良好的划线质量。 然后可以通过图案化掩模中的间隙等离子体蚀刻衬底，以在等离子体蚀刻期间用掩模保护IC来对IC进行分离。 然后可以在分离后溶解掩模的可溶性基底层，从而有助于去除该层。

公开(公告)号：US20230282498A1

公开(公告)日：2023-09-07

申请号：US18195234

申请日：2023-05-09

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI ,  Steven VERHAVERBEKE ,  Jean DELMAS ,  Han-Wen CHEN ,  Giback PARK

IPC: H01L21/67 ,  H01L21/48 ,  B23K26/0622 ,  B23K26/382

CPC classification number: H01L21/67121 ,  H01L21/486 ,  B23K26/0622 ,  B23K26/382 ,  H01L23/49827

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

公开(公告)号：US20230123795A1

公开(公告)日：2023-04-20

申请号：US17945861

申请日：2022-09-15

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Zhengping YAO ,  Mahendran CHIDAMBARAM ,  Kangkang WANG ,  Zhihong John LIN ,  Ludovic GODET ,  Visweswaren SIVARAMAKRISHNAN

IPC: B23K26/364 ,  B23K26/0622

Abstract: A method and apparatus for dicing optical devices from a substrate are described herein. The method includes the formation of a plurality of trenches using radiation pulses delivered to the substrate. The radiation pulses are delivered in a pattern to form trenches with varying depth as the trenches extend outward from a top surface of the optical device. The varying depth of the trenches provides edges of each of the optical devices which are slanted. The radiation pulses are UV radiation pulses and are delivered in bursts around the silhouette of the optical devices.

公开(公告)号：US20210346983A1

公开(公告)日：2021-11-11

申请号：US16871302

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Wei-Sheng LEI ,  Jeffrey L. FRANKLIN ,  Jean DELMAS ,  Han-Wen CHEN ,  Giback PARK ,  Steven VERHAVERBEKE

IPC: B23K26/0622 ,  B23K26/382 ,  B23K26/40 ,  H01L21/48 ,  H01L25/00

Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.

公开(公告)号：US20250022755A1

公开(公告)日：2025-01-16

申请号：US18898420

申请日：2024-09-26

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Brad EATON ,  Madhava Rao YALAMANCHILI ,  Saravjeet SINGH ,  Ajay KUMAR ,  James M. HOLDEN

IPC: H01L21/822 ,  B23K26/36 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20240021582A1

公开(公告)日：2024-01-18

申请号：US18360749

申请日：2023-07-27

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/522 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H05K1/144 ,  H01L23/5226 ,  H01L23/49586 ,  H01L25/50

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

公开(公告)号：US20220375787A1

公开(公告)日：2022-11-24

申请号：US17323381

申请日：2021-05-18

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Kurtis LESCHKIES ,  Roman GOUK ,  Giback PARK ,  Kyuil CHO ,  Tapash CHAKRABORTY ,  Han-Wen CHEN ,  Steven VERHAVERBEKE

IPC: H01L21/768 ,  H01L21/48

Abstract: The present disclosure relates to micro-via structures for interconnects in advanced wafer level semiconductor packaging. The methods described herein enable the formation of high-quality, low-aspect-ratio micro-via structures with improved uniformity, thus facilitating thin and small-form-factor semiconductor devices having high I/O density with improved bandwidth and power.

公开(公告)号：US20220139884A1

公开(公告)日：2022-05-05

申请号：US17578271

申请日：2022-01-18

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/522 ,  H01L23/495 ,  H01L25/00

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.