公开(公告)号：US12010242B2

公开(公告)日：2024-06-11

申请号：US16925723

申请日：2020-07-10

Applicant: Arm Limited

Inventor： Roberto Avanzi ,  Andreas Lars Sandberg ,  Michael Andrew Campbell ,  Matthias Lothar Boettcher ,  Prakash S. Ramrakhyani

IPC: H04L9/32 ,  G06F21/57 ,  G06F21/64 ,  H04W12/06 ,  G06F12/0875 ,  G06F12/14 ,  G06F21/79

CPC classification number: H04L9/3242 ,  G06F21/57 ,  G06F21/64 ,  H04W12/06 ,  G06F12/0875 ,  G06F12/1408 ,  G06F21/79

Abstract: To protect the integrity of data stored in a protected area of memory, data in the protected area of memory is retrieved in data blocks and an authentication code is associated with a memory granule contiguously comprising a first data block and a second data block. Calculation of the authentication code comprises a cryptographic calculation based on a first hash value determined from the first data block and a second hash value determined from the second data block. A hash value cache is provided to store hash values determined from data blocks retrieved from the protected area of the memory. When the first data block and its associated authentication code are retrieved from memory, a lookup for the second hash value in the hash value cache is performed, and a verification authentication code is calculated for the memory granule to which that data block belongs. The integrity of the first data block is contingent on the verification authentication code matching the retrieved authentication code.

公开(公告)号：US11657003B2

公开(公告)日：2023-05-23

申请号：US16778040

申请日：2020-01-31

Applicant: Arm Limited

Inventor： Ilias Vougioukas ,  Nikos Nikoleris ,  Andreas Lars Sandberg ,  Stephan Diestelhorst

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1027 ,  G06N5/04 ,  G06F9/48

CPC classification number: G06F12/1036 ,  G06F9/4806 ,  G06F12/1027 ,  G06N5/04 ,  G06F2212/681

Abstract: Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.

公开(公告)号：US11281434B2

公开(公告)日：2022-03-22

申请号：US16745808

申请日：2020-01-17

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Matthias Lothar Boettcher

IPC: G06F7/72

Abstract: An apparatus and method are provided for maintaining a counter value. The apparatus has first counter control circuitry for maintaining a first counter value representing a first portion of a hybrid counter value, and second counter control circuitry for maintaining a second counter value representing a second portion of the hybrid counter value, wherein the second portion is a higher order portion of the hybrid counter value than the first portion. The first counter control circuitry is arranged to maintain the first counter value as a binary value that indicates a magnitude of the first counter value, the first counter control circuitry comprising adder circuitry that is responsive to an adjustment value to update the first counter value by performing an addition operation to add the adjustment value to a current binary value of the first counter value, and to generate a carry out signal which is set when a carry out is generated by the addition operation. The second counter control circuitry is arranged to maintain the second counter value as a bit sequence having N discrete states, and is responsive to the carry out signal being set to transition the second counter value from the current discrete state to a new discrete state. This allows an arbitrary value to be used as the adjustment value, that is smaller than or equal to the maximum value of the first counter, whilst avoiding the need for the generation and handling of carry bits to be managed across the entire bit range of the hybrid counter value.

公开(公告)号：US11036639B2

公开(公告)日：2021-06-15

申请号：US15864062

申请日：2018-01-08

Applicant: ARM Limited

Inventor： Ricardo Daniel Queiros Alves ,  Nikos Nikoleris ,  Shidhartha Das ,  Andreas Lars Sandberg

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/0888

Abstract: A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. A set associative tag storage structure stores a tag value for each cache block, with that set associative tag storage structure being shared by the first and second data arrays. Control circuitry applies an access likelihood policy to determine, for each set, a subset of the cache blocks of that set to be stored within the first data array. Access circuitry is then responsive to an access request to perform a lookup operation within an identified set of the set associative tag storage structure overlapped with an access operation to access within the first data array the subset of the cache blocks for the identified set. In the event of a hit condition being detected that identifies a cache block present in the first data array, that access request is then processed using the cache block accessed within the first data array. If instead a hit condition is detected that identifies a cache block absent in the first data array, then a further access operation is performed to access the identified cache block within a selected way of the second data array. Such a cache structure provides a high performance and energy efficient mechanism for storing cached data.

公开(公告)号：US10929308B2

公开(公告)日：2021-02-23

申请号：US16169206

申请日：2018-10-24

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Nikos Nikoleris ,  Prakash S. Ramrakhyani ,  Stephan Diestelhorst

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/0808 ,  G06F12/06 ,  G06F3/06 ,  G06F13/16

Abstract: There is provided an apparatus that includes an input port to receive, from a requester, any one of: a lookup operation comprising an input address, and a maintenance operation. Maintenance queue circuitry stores a maintenance queue of at least one maintenance operation and address storage stores a translation between the input address and an output address in an output address space. In response to receiving the input address, the output address is provided in dependence on the maintenance queue. In response to storing the maintenance operation, the maintenance queue circuitry causes an acknowledgement to be sent to the requester. By providing a separate maintenance queue for performing the maintenance operation, there is no need for a requester to be blocked while maintenance is performed.

公开(公告)号：US10901884B2

公开(公告)日：2021-01-26

申请号：US15781979

申请日：2016-12-02

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Irenéus Johannes de Jong ,  Andreas Hansson

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/04

Abstract: Broadly speaking, embodiments of the present technique provide an apparatus and methods for improved wear-levelling in non-volatile memory (NVM) devices. In particular, the present wear-levelling techniques operate on small blocks within a memory device, at a finer scale/granularity than that used by common wear-levelling techniques which often remap large blocks (e.g. several kilobytes) of data.

公开(公告)号：US20240345962A1

公开(公告)日：2024-10-17

申请号：US18294668

申请日：2022-07-21

Applicant: Arm Limited

Inventor： Andreas Lars Sandberg ,  Ilias Vougioukas

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: There is provided address translation circuitry and a method for performing address translation. The address translation circuitry is responsive to receipt of a first address to perform an address translation between the first address and a second address by performing a predetermined maximum number of sequential lookups. The address translation circuitry is configured to support regular page tables comprising 2N entries and large page tables comprising 2N*M entries. The address translation circuitry is configured to: perform an intermediate lookup to retrieve information indicative of a sequentially next lookup address and page table size information and, when the page table size information indicates that the sequentially next lookup corresponds to one of the large page table and performing the sequentially next lookup would exceed the predetermined maximum number of sequential lookups, suppress subsequent lookups and generate the second address based on the information indicative of the sequentially next lookup address.

公开(公告)号：US20240220395A1

公开(公告)日：2024-07-04

申请号：US18554773

申请日：2022-02-10

Applicant: Arm Limited

Inventor： Parameshwarappa Anand Kumar Savanth ,  Sahan Sajeewa Hiniduma Udugama Gamage ,  Wei Wang ,  Andreas Lars Sandberg

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3656

Abstract: An apparatus and method are described for generating debug information. The apparatus has processing circuitry for executing a sequence of instructions that includes a plurality of debug information triggering instructions, and debug information generating circuitry for coupling to a debug port. On executing a given debug information triggering instruction, the processing circuitry is arranged to trigger the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction. The generated debug information signal is output from the debug port for reference by a debugger. The control parameter is such that the form of the debug information signal enables the debugger to determine a state of the processing circuitry when the given debug information triggering instruction was executed.

公开(公告)号：US11960945B2

公开(公告)日：2024-04-16

申请号：US17225674

申请日：2021-04-08

Applicant: Arm Limited

Inventor： Jonathan Curtis Beard ,  Curtis Glenn Dunham ,  Andreas Lars Sandberg ,  Roxana Rusitoru

IPC: G06F9/46 ,  G06F9/54 ,  G06F12/02 ,  G06F12/1009 ,  G06F15/78

CPC classification number: G06F9/546 ,  G06F9/542 ,  G06F12/023 ,  G06F12/1009 ,  G06F15/7817

Abstract: Message passing circuitry comprises lookup circuitry responsive to a producer request indicating message data provided on a target message channel by a producer node of a system-on-chip, to obtain, from a channel consumer information structure, selected channel consumer information associated with a given consumer node subscribing to the target message channel. Control circuitry writes the message data to a location associated with an address in a consumer-defined region of address space determined based on the selected channel consumer information. When an event notification condition is satisfied for the target message channel and the given consumer node, and an event notification channel is to be used, event notification data is written to a location associated with an address in a consumer-defined region of address space determined based on event notification channel consumer information associated with the event notification channel.

公开(公告)号：US20240078323A1

公开(公告)日：2024-03-07

申请号：US18446528

申请日：2023-08-09

Applicant: Arm Limited

Inventor： Alexander Klimov ,  Andreas Lars Sandberg ,  Roberto Avanzi

IPC: G06F21/60 ,  G06F21/74

CPC classification number: G06F21/602 ,  G06F21/74

Abstract: An apparatus comprises counter tree circuitry configured to store, in a first node of a counter tree, a representation of a parent counter value and in a second node of the counter tree, wherein the second node is a child node of the first node, an encrypted representation of two or more counter values. The encryption operation for forming the encrypted representation of the two or more counter values takes as an input the parent counter value. The apparatus also comprises integrity checking circuitry to check the integrity of an item of data retrieved from memory based on a comparison between a stored authentication code and a generated authentication code generated based on the item of data and a decrypted counter value determined from an encrypted representation of a counter value retrieved from the second node, decrypted using a parent counter value retrieved from the first node.