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公开(公告)号：US11444625B2
公开(公告)日：2022-09-13
申请号：US17103585
申请日：2020-11-24
Applicant: Arm Limited
Inventor： Benoit Labbe , Shidhartha Das , Thanusree Achuthan
Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.
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公开(公告)号：US20210143801A1
公开(公告)日：2021-05-13
申请号：US17157483
申请日：2021-01-25
Applicant: Arm Limited
Inventor： Philex Ming-Yan Fan , Parameshwarappa Anand Kumar Savanth , Benoit Labbe , Bal S. Sandhu , Pranay Prabhat , James Edward Myers
IPC: H03K3/0231 , H02M3/07
Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.
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Patent Agency Ranking
公开(公告)号：US11646740B2
公开(公告)日：2023-05-09
申请号：US17366904
申请日：2021-07-02
Applicant: Arm Limited
Inventor： Benoit Labbe
IPC: H03L7/081 , G01R31/317
CPC classification number: H03L7/081 , G01R31/31709
Abstract: In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.
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公开(公告)号：US20230006678A1
公开(公告)日：2023-01-05
申请号：US17366904
申请日：2021-07-02
Applicant: Arm Limited
Inventor： Benoit Labbe
IPC: H03L7/081 , G01R31/317
Abstract: In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.
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公开(公告)号：US20210026389A1
公开(公告)日：2021-01-28
申请号：US16520112
申请日：2019-07-23
Applicant: Arm Limited
Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.
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公开(公告)号：US10886847B1
公开(公告)日：2021-01-05
申请号：US16441228
申请日：2019-06-14
Applicant: Arm Limited
Inventor： Benoit Labbe , Graham Peter Knight , Philex Ming-Yan Fan
Abstract: Various implementations described herein are directed to a device having a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for adjusting the output voltage.
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公开(公告)号：US20200089266A1
公开(公告)日：2020-03-19
申请号：US16130938
申请日：2018-09-13
Applicant: Arm Limited
IPC: G05F3/24 , G05F1/46 , G11C5/14 , G11C11/4074
Abstract: Briefly, embodiments of claimed subject matter relate to comparison of a signal amplitude, such as a signal originating from a battery, for example, with a reference signal. A reference signal may be generated via body-biasing of one or more transistors, for example, which permit operation of the one or more transistors in a sub-threshold state, in which current through the one or more transistors comprises an exponential relationship to an applied voltage. Thus, at least in particular embodiments, detection of low battery voltage or battery overvoltage may be performed utilizing only a very small amount of electrical power
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