公开(公告)号：US11520658B2

公开(公告)日：2022-12-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton Irby ,  Wendy Arnott Elsasser ,  Mudit Bhargava ,  Yew Keong Chong ,  George McNeil Lattimore ,  James Dennis Dodrill

IPC: G06F11/10 ,  G11C5/14 ,  G11C7/10 ,  G11C29/12 ,  G06N20/00

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US10020031B2

公开(公告)日：2018-07-10

申请号：US15401588

申请日：2017-01-09

Applicant: ARM Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Gus Yeung ,  James Dennis Dodrill

IPC: G11C8/18 ,  G11C7/10 ,  G11C29/50 ,  G11C5/14 ,  G11C8/06 ,  G11C29/02 ,  G11C29/00

CPC classification number: G11C7/1012 ,  G11C5/141 ,  G11C8/06 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/702

Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

公开(公告)号：US09892220B2

公开(公告)日：2018-02-13

申请号：US15456634

申请日：2017-03-13

Applicant: ARM Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Karen Lee Delk ,  Lena Ahlen ,  James Dennis Dodrill

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A static timing analysis method and apparatus that determine an expected design condition surrounding a target cell in an integrated circuit design. A derate adjustment is determined based on the expected design condition for a target cell and a timing derate, representing variation in propagation delay for a default design condition, is then adjusted based on the derate adjustment. An expected timing of a signal path including the target cell is determined based on the adjusted timing derate. The derate adjustment may be determined based on simulated variance of the propagation delay through the target cell for the expected design condition. This approach avoids unnecessary optimism or pessimism in the timing derate, which reduces the number of false positive or false negative detections of timing violations in the static timing analysis.

公开(公告)号：US09651620B2

公开(公告)日：2017-05-16

申请号：US14531512

申请日：2014-11-03

Applicant: ARM LIMITED

Inventor： Ramesh Manohar ,  James Dennis Dodrill

IPC: G01R27/28 ,  G01R31/3183 ,  H03K3/03

CPC classification number: G01R31/318328 ,  H03K3/0315

Abstract: A measurement circuit and method is provided for generating an oscillating output signal used to derive timing information. The measurement circuit includes a ring oscillator having a plurality of unit cells, where each unit cell comprises at least a storage element whose output signal is used to determine a clock input signal for an adjacent unit cell within the ring oscillator. Control circuitry performs a control operation to control either a set function or a reset function of the storage element in each of the unit cells, in dependence on set or reset signals input to the control circuitry. Oscillation initiation circuitry is used to assert a clock input signal to the storage element in a first unit cell in order to initiate generation of the oscillating output signal, and the control circuitry then performs the control operation in order to control a value of the output signal of the storage element in each unit cell so as to cause the oscillating output signal to be maintained. Such an approach provides a particularly simple and efficient mechanism for deriving timing information for various circuit blocks that include a storage element.

公开(公告)号：US09479147B2

公开(公告)日：2016-10-25

申请号：US14531419

申请日：2014-11-03

Applicant: ARM LIMITED

Inventor： Satheesh Balasubramanian ,  James Dennis Dodrill

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/35625 ,  H03K3/0372

Abstract: A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.

Abstract translation: 提供了同步器触发器，其能够更好地响应不为必要的建立或保持时间提供的输入值。 触发器包括锁存器，其包括用于根据节点处的输入信号的值产生第一信号和信号的反相器电路。 时钟反相器包括连接在第一参考电压源和中间节点之间的第一开关和连接在中间节点和第二参考电压源之间的第二开关。 第一开关由第一信号控制，第二开关由第二信号控制，以在中间节点产生输出信号。

公开(公告)号：US20160124045A1

公开(公告)日：2016-05-05

申请号：US14531512

申请日：2014-11-03

Applicant: ARM LIMITED

Inventor： Ramesh MANOHAR ,  James Dennis Dodrill

IPC: G01R31/3183 ,  H03K3/03

CPC classification number: G01R31/318328 ,  H03K3/0315

Abstract: A measurement circuit and method is provided for generating an oscillating output signal used to derive timing information. The measurement circuit includes a ring oscillator having a plurality of unit cells, where each unit cell comprises at least a storage element whose output signal is used to determine a clock input signal for an adjacent unit cell within the ring oscillator. Control circuitry performs a control operation to control either a set function or a reset function of the storage element in each of the unit cells, in dependence on set or reset signals input to the control circuitry. Oscillation initiation circuitry is used to assert a clock input signal to the storage element in a first unit cell in order to initiate generation of the oscillating output signal, and the control circuitry then performs the control operation in order to control a value of the output signal of the storage element in each unit cell so as to cause the oscillating output signal to be maintained. Such an approach provides a particularly simple and efficient mechanism for deriving timing information for various circuit blocks that include a storage element.

Abstract translation: 提供了一种用于产生用于导出定时信息的振荡输出信号的测量电路和方法。 测量电路包括具有多个单位单元的环形振荡器，其中每个单位单元至少包括存储元件，其输出信号用于确定环形振荡器内相邻单元的时钟输入信号。 控制电路执行控制操作，以根据输入到控制电路的设置或复位信号来控制每个单位单元中的存储元件的设定功能或复位功能。 振荡启动电路用于将时钟输入信号断言到第一单元中的存储元件，以便产生振荡输出信号，然后控制电路执行控制操作，以便控制输出信号的值 的每个单位单元中的存储元件，以便保持振荡输出信号。 这种方法提供了一种用于导出包括存储元件的各种电路块的定时信息的特别简单和有效的机制。