公开(公告)号：US20160350114A1

公开(公告)日：2016-12-01

申请号：US15088368

申请日：2016-04-01

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3838 ,  G06F9/3859 ,  G06F9/3863

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

Abstract translation: 一种装置具有寄存器重命名电路，用于将由指令指定的架构寄存器说明符映射到识别物理寄存器的物理寄存器说明符。 恢复表识别架构寄存器说明符和先前映射的物理寄存器说明符之间的至少一个恢复映射。 寄存器保留电路指示一个或多个保留寄存器说明符。 响应于检测到当该指令或较旧的指令仍然可能读取寄存器时已经提交了对应于恢复映射的推测指令时，寄存器保留电路将该恢复映射的物理寄存器说明符指示为保留。

公开(公告)号：US09424045B2

公开(公告)日：2016-08-23

申请号：US13752621

申请日：2013-01-29

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Frederic Claude Marie Piry ,  Albin Pierick Tonnerre

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract translation: 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。

公开(公告)号：US09286069B2

公开(公告)日：2016-03-15

申请号：US13723974

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Cédric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30141 ,  G06F9/3857

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier. Write port usage is tracked by a write port usage scoreboard 26 which is both read and updated by the bypass circuitry 22 when re-arbitrating write port availability partway through a floating point multiplication instruction passing along the pipeline 14.

Abstract translation: 在处理流水线14内，发布控制电路12用于在将浮点乘法指令发布到浮点流水线14时仲裁写端口的可用性。如果不是以冲零模式运行，则根据产生的非正规输出操作数 处理可能或可能不需要。 在需要进行异常处理的问题上做出悲观的假设，因此，保留的写入端口是在开始周期之后的第一预定数量的处理周期，以考虑使用异常处理流水线级20。沿着处理流水线14 ，状态变为可用，其指示是否实际需要异常处理。 如果不需要异常处理并且写入端口可用于处理周期之前，则旁路电路22用于绕过异常处理流水线级20，使得输出操作数将被更早地写入一个处理周期的寄存器组16。 写端口使用记录板26由写入端口使用记分板26跟踪，当通过沿管线14传送的浮点乘法指令重新协商写入端口可用性时，旁路电路22读取和更新。

公开(公告)号：US10042640B2

公开(公告)日：2018-08-07

申请号：US15076889

申请日：2016-03-22

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec ,  Cedric Denis Robert Airaud

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/52 ,  G06F8/41

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialization instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialization instruction SSI added to a second issue queue 10. The master serialization instruction MSI manages serialization relative to the instructions within the first issue queue 8. The slave serialization instruction SSI manages serialization relative to the instructions within the second issue queue 10. The master serialization instruction MSI and the slave serialization instruction SSI are removed when both have met their serialization conditions and are respectively the oldest instructions within their issue queues.

公开(公告)号：US09400655B2

公开(公告)日：2016-07-26

申请号：US13847892

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Guillaume Schon ,  Cedric Denis Robert Airaud ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract translation: 用于处理装置的注册重命名电路，被配置为处理来自指定集合的​​指令集的指令流，所述指令集指定来自架构的一组寄存器。 该装置包括被配置为存储由处理装置处理的数据值的寄存器的物理组。 寄存器重命名电路被配置为从指令解码器接收操作流，并将要由操作流写入的寄存器映射到当前可用的寄存器的物理组内的物理寄存器。 寄存器重命名电路包括寄存器释放电路，其被配置为当满足第一组条件时释放已经被映射到寄存器的物理寄存器，并且当第二组存储器被释放时已被映射到附加寄存器的物理寄存器 条件得到满足。

公开(公告)号：US09170819B2

公开(公告)日：2015-10-27

申请号：US13737137

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Nicolas Chaussade ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Cedric Denis Robert Airaud

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30072 ,  G06F9/3826

Abstract: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid.

Abstract translation: 数据处理装置包括第一和第二处理电路。 由第二处理电路执行的条件指令可以具有取决于由第一处理电路维护的多组条件信息之一的结果。 第一转发路径可将来自第一处理电路的条件信息集合转发到第二处理电路的处理流水线的预定流水线级。 请求路径可以将来自第二处理电路的请求信号发送到第一处理电路，该请求信号指示当条件指令处于预定流水线阶段时尚未有效的请求的条件信息集合。 当信息变得有效时，第二转发路径可以将所请求的条件信息集合转发到后续流水线级。

公开(公告)号：US20140181478A1

公开(公告)日：2014-06-26

申请号：US13723974

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Cédric Denis Robert AIRAUD ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30141 ,  G06F9/3857

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier. Write port usage is tracked by a write port usage scoreboard 26 which is both read and updated by the bypass circuitry 22 when re-arbitrating write port availability partway through a floating point multiplication instruction passing along the pipeline 14.

Abstract translation: 在处理流水线14内，发布控制电路12用于在将浮点乘法指令发布到浮点流水线14时仲裁写端口的可用性。如果不是以冲零模式工作，则根据产生的非正规输出操作数 处理可能或可能不需要。 在需要进行异常处理的问题上做出悲观的假设，因此，保留的写入端口是在开始周期之后的第一预定数量的处理周期，以考虑使用异常处理流水线级20。沿着处理流水线14 ，状态变为可用，其指示是否实际需要异常处理。 如果不需要异常处理并且写入端口可用于处理周期之前，则旁路电路22用于绕过异常处理流水线级20，使得输出操作数将被更早地写入一个处理周期的寄存器组16。 写端口使用记录板26由写入端口使用记分板26跟踪，当通过沿管线14传送的浮点乘法指令重新协商写入端口可用性时，旁路电路22读取和更新。