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    Writing zero data
    14.
    发明授权
    Writing zero data 有权

    公开(公告)号：US11188377B2

    公开(公告)日：2021-11-30

    申请号：US16592979

    申请日：2019-10-04

    Applicant: Arm Limited

    Inventor： Jamshed Jalal ,  Mark David Werkheiser ,  Phanindra Kumar Mannava ,  Bruce James Mathewson

    IPC: G06F12/0891 ,  G06F12/0808 ,  G06F9/46 ,  G06F9/455 ,  G06F13/40 ,  G06F12/10 ,  G06F9/38

    Abstract: Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.

    Forwarding responses to snoop requests
    15.
    发明授权
    Forwarding responses to snoop requests 有权

    公开(公告)号：US11159636B2

    公开(公告)日：2021-10-26

    申请号：US15427384

    申请日：2017-02-08

    Applicant: ARM Limited

    Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Klas Magnus Bruce

    IPC: H04L29/08 ,  G06F12/0831

    Abstract: A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. Transmitting circuitry transmits a response to the snoop request and cache circuitry caches at least one data value. When forwarding is to occur and the at least one data value includes the requested data, the response includes the requested data and the transmitting circuitry transmits the response to the requesting node.

    Interconnect circuitry and a method of operating such interconnect circuitry
    16.
    发明授权
    Interconnect circuitry and a method of operating such interconnect circuitry 有权

    公开(公告)号：US10963409B2

    公开(公告)日：2021-03-30

    申请号：US15241461

    申请日：2016-08-19

    Applicant: ARM Limited

    Inventor： Rowan Nigel Naylor ,  Phanindra Kumar Mannava ,  Bruce James Mathewson

    IPC: G06F13/362 ,  H04L12/707

    Abstract: An interconnect circuit, and method of operation of such an interconnect circuit, are provided. The interconnect circuitry has a first interface for coupling to a master device and a second interface for coupling to a slave device. Transactions are performed between the master device and the slave device, where each transaction comprises or more transfers, and each transfer comprises a request and a response. A first connection path between the first interface and the second interface is provided that comprises a first plurality of pipeline stages. The first connection path forms a default path for propagation of the requests and responses of the transfers. A second connection path is also provided between the first interface and the second interface that comprises a second plurality of pipeline stages, where the second plurality is less than the first plurality. Path selection circuitry is then used to determine presence of a fast path condition. In the presence of the fast path condition, the path selection circuitry causes at least one of the request and the response for one or more transfers to be propagated via the second connection path. This can significantly reduce the latency associated with the handling of transfers within the interconnect circuitry, and hence improves the overall performance of the interconnect circuitry.

    Read transaction tracker lifetimes in a coherent interconnect system
    17.
    发明授权
    Read transaction tracker lifetimes in a coherent interconnect system 有权

    公开(公告)号：US10795820B2

    公开(公告)日：2020-10-06

    申请号：US15427435

    申请日：2017-02-08

    Applicant: ARM Limited

    Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Tushar P Ringe

    IPC: G06F12/0831 ,  G06F11/14

    Abstract: Apparatus and a corresponding method of operating the apparatus, in a coherent interconnect system comprising a requesting master device and a data-storing slave device, are provided. The apparatus maintains records of coherency protocol transactions received from the requesting master device whilst completion of the coherency protocol transactions are pending and is responsive to reception of a read transaction from the requesting master device for a data item stored in the data-storing slave device to issue a direct memory transfer request to the data-storing slave device. A read acknowledgement trigger is added to the direct memory transfer request and in response to reception of a read acknowledgement signal from the data-storing slave device a record created by reception of the read transaction is updated corresponding to completion of the direct memory transfer request. The lifetime that the apparatus needs to maintain the record is thus reduced, despite the read transaction being satisfied by a direct memory transfer. A corresponding data-storing slave device and method of operating the data-storing slave device are also provided.

    Cache maintenance operations in a data processing system
    18.
    发明授权
    Cache maintenance operations in a data processing system 有权

    公开(公告)号：US10783080B2

    公开(公告)日：2020-09-22

    申请号：US16173213

    申请日：2018-10-29

    Applicant: Arm Limited

    Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal ,  Paul Gilbert Meyer

    IPC: G06F12/08 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/1009 ,  G06F3/06 ,  G06F9/52

    Abstract: An interconnect system and method of operating the system are disclosed. A master device has access to a cache and a slave device has an associated data storage device for long-term storage of data items. The master device can initiate a cache maintenance operation in the interconnect system with respect to a data item temporarily stored in the cache causing action to be taken by the slave device with respect to storage of the data item in the data storage device. For long latency operations the master device can issue a separated cache maintenance request specifying the data item and the slave device. In response an intermediate device signals an acknowledgment response indicating that it has taken on responsibility for completion of the cache maintenance operation and issues the separated cache maintenance request to the slave device. The slave device signals the acknowledgement response to the intermediate device and on completion of the cache maintenance operation with respect to the data item stored in the data storage device signals a completion response to the master device.

    Runtime configuration of a data processing system
    19.
    发明授权
    Runtime configuration of a data processing system 有权

    公开(公告)号：US10732854B2

    公开(公告)日：2020-08-04

    申请号：US15977153

    申请日：2018-05-11

    Applicant: Arm Limited

    Inventor： Bruce James Mathewson ,  Carlos Garcia-Tobin ,  Phanindra Kumar Mannava ,  Thanunathan Rangarajan

    IPC: G06F13/00 ,  G06F13/36 ,  G06F3/06 ,  G06F13/362 ,  G06F9/4401

    Abstract: A data processing system and a method of runtime configuration of the data processing system are disclosed. The data processing system comprises a plurality of home nodes, and for a data store associated with a slave node in the data processing system, for each home node of the plurality of home nodes a modified size of the data store is determined. The modified size is based on a storage capacity of the data store and at least one additional property of the data processing system. A chosen home node of the plurality of home nodes is selected which satisfies a minimization criterion for the modified size, and the chosen home node is paired with the slave node.

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