公开(公告)号：US08035141B2

公开(公告)日：2011-10-11

申请号：US12607104

申请日：2009-10-28

申请人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

IPC分类号： H01L29/76

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

摘要翻译： 公开了一种包括双层nFET嵌入式应力元件的半导体结构。 双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。 双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变 。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。 双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。 双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

公开(公告)号：US07989298B1

公开(公告)日：2011-08-02

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20110183486A1

公开(公告)日：2011-07-28

申请号：US12692859

申请日：2010-01-25

申请人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

发明人： Kevin K. Chan ,  Brian J. Greene ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Thomas S. Kanarsky ,  Jophy S. Koshy ,  Kevin McStay ,  Dae-Gyu Park ,  Johan W. Weijtmans ,  Frank B. Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.

摘要翻译： 提供半导体器件和制造该器件的方法。 该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。 使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。 使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。 随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。 然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

公开(公告)号：US20110171788A1

公开(公告)日：2011-07-14

申请号：US12684997

申请日：2010-01-11

申请人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

发明人： Kevin K. Chan ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66772

摘要： A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.

摘要翻译： 一种形成场效应器件的方法包括在绝缘体上硅层（SOI）上形成栅极部分，在邻近栅极部分的SOI层上形成第一间隔元件，在SOI层上沉积间隔物材料层， 第一隔离构件和栅极部分，去除间隔物材料层的部分，以在与第一间隔件相邻的SOI层上形成第二间隔件，通过将离子注入到SOI层上形成源极区域和漏极区域 SOI层，并蚀刻以除去第二间隔件。

公开(公告)号：US07888264B2

公开(公告)日：2011-02-15

申请号：US12814942

申请日：2010-06-14

申请人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

发明人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

IPC分类号： H01L21/44

CPC分类号： H01L29/66507 ,  H01L29/6653 ,  H01L29/7833

摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

摘要翻译： 提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。 根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。 此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

公开(公告)号：US07816224B2

公开(公告)日：2010-10-19

申请号：US12042936

申请日：2008-03-05

申请人： Kevin K. Chan ,  Jakub Kedzierski ,  Raymond M. Sicina

发明人： Kevin K. Chan ,  Jakub Kedzierski ,  Raymond M. Sicina

IPC分类号： H01L21/76

CPC分类号： H01L29/66628 ,  H01L21/7624 ,  H01L29/66772 ,  H01L29/78654

摘要： In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.

摘要翻译： 在一个实施例中，本发明是用于制造绝缘体上的超薄硅的方法。 用于制造绝缘体上的超薄硅的方法的一个实施例包括提供硅层，在第一温度下使硅层与至少一种反应气体饱和，第一温度足够低以基本上防止发生任何涉及 反应气体，并将第一温度升至第二温度，第二温度大约为反应气体的解离温度。

公开(公告)号：US20100001260A1

公开(公告)日：2010-01-07

申请号：US12544436

申请日：2009-08-20

申请人： Joerg Appenzeller ,  Phaedon Avouris ,  Kevin K. Chan ,  Philip G. Collins ,  Richard Martel ,  Hon-Sum Philip Wong

发明人： Joerg Appenzeller ,  Phaedon Avouris ,  Kevin K. Chan ,  Philip G. Collins ,  Richard Martel ,  Hon-Sum Philip Wong

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L51/0516 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0545 ,  Y10S977/842 ,  Y10S977/938 ,  Y10S977/94

摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

摘要翻译： 自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极 碳纳米管的一部分，通过电介质膜与碳纳米管分离。

公开(公告)号：US07485518B2

公开(公告)日：2009-02-03

申请号：US11684855

申请日：2007-03-12

申请人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

发明人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

IPC分类号： H01L21/336

CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

公开(公告)号：US20080268600A1

公开(公告)日：2008-10-30

申请号：US12131973

申请日：2008-06-03

申请人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

发明人： Kevin K. Chan ,  Christian Lavoie ,  Kern Rim

IPC分类号： H01L21/336

CPC分类号： H01L29/66507 ,  H01L29/6653 ,  H01L29/7833

摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

摘要翻译： 提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。 根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。 此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

公开(公告)号：US07253065B2

公开(公告)日：2007-08-07

申请号：US10956851

申请日：2004-10-01

申请人： Joerg Appenzeller ,  Phaedon Avouris ,  Kevin K. Chan ,  Philip G. Collins ,  Richard Martel ,  Hon-Sum Philip Wong

发明人： Joerg Appenzeller ,  Phaedon Avouris ,  Kevin K. Chan ,  Philip G. Collins ,  Richard Martel ,  Hon-Sum Philip Wong

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L51/0516 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0545 ,  Y10S977/842 ,  Y10S977/938 ,  Y10S977/94

摘要： A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

摘要翻译： 自对准碳纳米管场效应晶体管半导体器件分别包括沉积在基板上的碳纳米管，分别形成在碳纳米管的第一端和第二端的源极和漏极，以及基本上形成的栅极 碳纳米管的一部分，通过电介质膜与碳纳米管分离。