Methods of forming a doped semiconductor thin film, doped semiconductor thin film structures, doped silane compositions, and methods of making such compositions
    11.
    发明授权
    Methods of forming a doped semiconductor thin film, doped semiconductor thin film structures, doped silane compositions, and methods of making such compositions 有权
    形成掺杂半导体薄膜,掺杂半导体薄膜结构,掺杂硅烷组合物的方法和制备这种组合物的方法

    公开(公告)号:US08372194B1

    公开(公告)日:2013-02-12

    申请号:US12020481

    申请日:2008-01-25

    IPC分类号: C09D183/16

    摘要: Methods for forming doped silane and/or semiconductor thin films, doped liquid phase silane compositions useful in such methods, and doped semiconductor thin films and structures. The composition is generally liquid at ambient temperatures and includes a Group IVA atom source and a dopant source. By irradiating a doped liquid silane during at least part of its deposition, a thin, substantially uniform doped oligomerized/polymerized silane film may be formed on a substrate. Such irradiation is believed to convert the doped silane film into a relatively high-molecular weight species with relatively high viscosity and relatively low volatility, typically by cross-linking, isomerization, oligomerization and/or polymerization. A film formed by the irradiation of doped liquid silanes can later be converted (generally by heating and annealing/recrystallization) into a doped, hydrogenated, amorphous silicon film or a doped, at least partially polycrystalline silicon film suitable for electronic devices. Thus, the present invention enables use of high throughput, low cost equipment and techniques for making doped semiconductor films of commercial quality and quantity from doped “liquid silicon.”

    摘要翻译: 用于形成掺杂的硅烷和/或半导体薄膜的方法,用于这种方法的掺杂的液相硅烷组合物,以及掺杂的半导体薄膜和结构。 组合物在环境温度下通常是液体,并且包括IVA族原子源和掺杂剂源。 通过在其沉积的至少一部分期间照射掺杂的液体硅烷,可以在衬底上形成薄的,基本上均匀的掺杂的低聚/聚合的硅烷膜。 据信这种照射将掺杂的硅烷膜转化成相对高分子量的物质,具有相对较高的粘度和较低挥发性,通常通过交联,异构化,低聚和/或聚合。 通过掺杂的液体硅烷的照射形成的膜可以随后通过加热和退火/重结晶转化成掺杂的,氢化的非晶硅膜或适用于电子器件的掺杂的至少部分多晶的硅膜。 因此,本发明能够使用高通量,低成本的设备和技术来制造掺杂的液态硅具有商业质量和数量的掺杂半导体膜。

    Methods of forming a doped semiconductor thin film, doped semiconductor thin film structures, doped silane compositions, and methods of making such compositions
    13.
    发明授权
    Methods of forming a doped semiconductor thin film, doped semiconductor thin film structures, doped silane compositions, and methods of making such compositions 有权
    形成掺杂半导体薄膜,掺杂半导体薄膜结构,掺杂硅烷组合物的方法和制备这种组合物的方法

    公开(公告)号:US07981482B1

    公开(公告)日:2011-07-19

    申请号:US11455976

    申请日:2006-06-19

    IPC分类号: C08J7/06

    摘要: Methods for forming doped silane and/or semiconductor thin films, doped liquid phase silane compositions useful in such methods, and doped semiconductor thin films and structures. The composition is generally liquid at ambient temperatures and includes a Group IVA atom source and a dopant source. By irradiating a doped liquid silane during at least part of its deposition, a thin, substantially uniform doped oligomerized/polymerized silane film may be formed on a substrate. Such irradiation is believed to convert the doped silane film into a relatively high-molecular weight species with relatively high viscosity and relatively low volatility, typically by cross-linking, isomerization, oligomerization and/or polymerization. A film formed by the irradiation of doped liquid silanes can later be converted (generally by heating and annealing/recrystallization) into a doped, hydrogenated, amorphous silicon film or a doped, at least partially polycrystalline silicon film suitable for electronic devices. Thus, the present invention enables use of high throughput, low cost equipment and techniques for making doped semiconductor films of commercial quality and quantity from doped “liquid silicon.”

    摘要翻译: 用于形成掺杂的硅烷和/或半导体薄膜的方法,用于这种方法的掺杂的液相硅烷组合物,以及掺杂的半导体薄膜和结构。 组合物在环境温度下通常是液体,并且包括IVA族原子源和掺杂剂源。 通过在其沉积的至少一部分期间照射掺杂的液体硅烷,可以在衬底上形成薄的,基本上均匀的掺杂的低聚/聚合的硅烷膜。 据信这种照射将掺杂的硅烷膜转化成相对高分子量的物质,具有相对较高的粘度和较低挥发性,通常通过交联,异构化,低聚和/或聚合。 通过掺杂的液体硅烷的照射形成的膜可以随后通过加热和退火/重结晶转化成掺杂的,氢化的非晶硅膜或适用于电子器件的掺杂的至少部分多晶的硅膜。 因此,本发明能够使用高通量,低成本的设备和技术来制造掺杂的“液态硅”具有商业质量和数量的掺杂半导体膜。

    PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR
    16.
    发明申请
    PRINTED, SELF-ALIGNED, TOP GATE THIN FILM TRANSISTOR 审中-公开
    打印,自对准,顶盖薄膜晶体管

    公开(公告)号:US20140299883A1

    公开(公告)日:2014-10-09

    申请号:US14311044

    申请日:2014-06-20

    IPC分类号: H01L29/786

    摘要: A self-aligned top-gate thin film transistor (TFT) and a method of forming such a thin film transistor, by forming a semiconductor thin film layer; printing a doped glass pattern thereon, a gap in the doped glass pattern defining a channel region of the TFT; forming a gate electrode on or over the channel region, the gate electrode comprising a gate dielectric film and a gate conductor thereon; and diffusing a dopant from the doped glass pattern into the semiconductor thin film layer.

    摘要翻译: 一种自对准顶栅薄膜晶体管(TFT)和通过形成半导体薄膜层形成这种薄膜晶体管的方法; 在其上印刷掺杂的玻璃图案,所述掺杂玻璃图案中的间隙限定所述TFT的沟道区域; 在沟道区域上或上方形成栅电极,栅电极在其上包括栅介质膜和栅极导体; 并且将掺杂剂从掺杂的玻璃图案扩散到半导体薄膜层中。

    Methods of making metal silicide contacts, interconnects, and/or seed layers
    18.
    发明授权
    Methods of making metal silicide contacts, interconnects, and/or seed layers 有权
    制造金属硅化物接触,互连和/或种子层的方法

    公开(公告)号:US08158518B2

    公开(公告)日:2012-04-17

    申请号:US12175450

    申请日:2008-07-17

    IPC分类号: H01L21/44

    摘要: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.

    摘要翻译: 公开了使用包含硅化物形成金属的油墨形成触点(和任选的局部互连)的方法,诸如二极管和/或包括这种触点的晶体管的电气器件,(可选的)局部互连)以及用于形成这种器件的方法。 形成接触的方法包括将硅化物形成金属的油墨沉积到暴露的硅表面上,干燥油墨以形成形成硅化物的金属前体,以及加热形成硅化物的金属前体和硅表面以形成金属硅化物 联系。 任选地,可以将金属前体油墨选择性地沉积到与暴露的硅表面相邻的电介质层上,以形成含金属互连。 此外,一个或多个体导电金属可以沉积在剩余的金属前体油墨和/或介电层上。 可以使用这种印刷的接触和/或局部互连来制造电子器件,例如二极管和晶体管。 金属墨水可以同时印刷以用于接触以及局部互连,或者替代地,如果需要用于接触和互连线的不同金属,印刷金属可以用作其它金属的无电沉积的种子 。 这种方法有利地减少了处理步骤的数量,并且不一定需要任何蚀刻。

    Printed Non-Volatile Memory
    20.
    发明申请
    Printed Non-Volatile Memory 有权
    印刷非易失性存储器

    公开(公告)号:US20100163962A1

    公开(公告)日:2010-07-01

    申请号:US12723542

    申请日:2010-03-12

    IPC分类号: H01L29/788

    摘要: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

    摘要翻译: 公开了一种非易失性存储器单元,其具有在相同水平位置处并且间隔开预定距离的第一和第二半导体岛,所述第一半岛具有提供控制栅极和所述第二半岛岛提供源极和漏极端子; 在所述第一半导体岛的至少一部分上的栅介质层; 在所述第二半导体岛的至少一部分上的隧道电介质层; 至少部分栅极电介质层和隧道电介质层上的浮栅; 以及与控制栅极以及源极和漏极端子电接触的金属层。 在一个有利的实施例中,可以使用“全印刷”工艺技术来制造非易失性存储单元。