公开(公告)号：US20180053497A1

公开(公告)日：2018-02-22

申请号：US15683592

申请日：2017-08-22

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Wai Laing Lee ,  Jianping Wen

IPC: G10K11/178

CPC classification number: G10K11/178 ,  G10K11/17853 ,  G10K11/17873 ,  G10K11/17875 ,  G10K11/17879 ,  G10K2210/3016 ,  G10K2210/3026 ,  G10K2210/3027 ,  G10K2210/3028 ,  H04R2460/01

Abstract: An adaptive noise canceling system can include a noise cancellation processor having an audio input for receiving an input audio signal, a microphone input structured to receive one or more microphone signals from a monitored environment, and a filter processor structured to produce a filtering function based on one or more filter parameters. The system can also include an adaptivity processor structured to change the one or more filter parameters in the noise cancellation processor based on a changing operating environment of the adaptive noise canceling system.

公开(公告)号：US20190245551A1

公开(公告)日：2019-08-08

申请号：US16386188

申请日：2019-04-16

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/1038 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US20190173482A1

公开(公告)日：2019-06-06

申请号：US16173398

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/10 ,  H03M1/44

CPC classification number: H03M1/462 ,  H03M1/1033 ,  H03M1/188 ,  H03M1/447 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

公开(公告)号：US10177779B2

公开(公告)日：2019-01-08

申请号：US15849227

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Garry N. Link ,  Jianping Wen

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/44 ,  H03M1/06 ,  H03M1/08

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.

公开(公告)号：US10096312B2

公开(公告)日：2018-10-09

申请号：US15683592

申请日：2017-08-22

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Wai Laing Lee ,  Jianping Wen

IPC: H03B29/00 ,  G10K11/178

Abstract: An adaptive noise canceling system can include a noise cancellation processor having an audio input for receiving an input audio signal, a microphone input structured to receive one or more microphone signals from a monitored environment, and a filter processor structured to produce a filtering function based on one or more filter parameters. The system can also include an adaptivity processor structured to change the one or more filter parameters in the noise cancellation processor based on a changing operating environment of the adaptive noise canceling system.

公开(公告)号：US20180278262A1

公开(公告)日：2018-09-27

申请号：US15991871

申请日：2018-05-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/1038 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US20180183457A1

公开(公告)日：2018-06-28

申请号：US15849234

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/44 ,  H03M1/08

CPC classification number: H03M1/462 ,  H03M1/0678 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/442 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US09985640B1

公开(公告)日：2018-05-29

申请号：US15793839

申请日：2017-10-25

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Gordon Ueki

IPC: H03M1/38 ,  H03M1/10 ,  H03M1/46

CPC classification number: H03M1/1009 ,  H03M1/462 ,  H03M1/466

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

公开(公告)号：US20190222219A1

公开(公告)日：2019-07-18

申请号：US16159498

申请日：2018-10-12

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Garry Link ,  Wai Laing Lee

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/46 ,  H03M1/06 ,  H03M1/40

CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804 ,  H05K999/99

Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.

公开(公告)号：US10135455B2

公开(公告)日：2018-11-20

申请号：US15799812

申请日：2017-10-31

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Garry Link ,  Wai Laing Lee

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/46 ,  H03M1/40 ,  H03M1/06 ,  H03M1/80

Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.