Shift register unit, driving circuit, display device and driving method

    公开(公告)号:US11308854B2

    公开(公告)日:2022-04-19

    申请号:US16642140

    申请日:2019-03-22

    Inventor: Can Zheng

    Abstract: A shift register unit, a driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit, a first control circuit, and a second control circuit. The first input circuit is electrically connected to a first node, and is configured to transmit an input signal to the first node; the second input circuit is electrically connected to the first node and a second node, and is configured to control a level of the second node; the first control circuit is electrically connected to the second node and a third node, and is configured to control a level of the third node; and the output circuit is electrically connected to the third node and an output terminal, and is configured to output an output signal to the output terminal.

    Shift register unit, driving method, gate driving circuit and display device

    公开(公告)号:US11232734B2

    公开(公告)日:2022-01-25

    申请号:US16964465

    申请日:2019-09-25

    Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes a first gate driving output circuit and a second gate driving output circuit. The first gate driving output circuit is used to output a first gate driving signal through the first gate driving signal output terminal; the second gate driving output circuit is used to generate a second gate driving signal outputted simultaneously with the first gate driving signal based on the first gate driving signal, a first clock signal and a second clock signal. In the present disclosure, the second gate driving output circuit is added, the first gate driving signal, the first clock signal, and the second clock signal are used to generate an inverted second gate driving signal, so that positive and negative switching control signals are generated by one stage of shift register unit.

    GATE DRIVING CIRCUIT, GATE DRIVING METHOD, FOLDABLE DISPLAY PANEL, AND DISPLAY APPARATUS

    公开(公告)号:US20210217339A1

    公开(公告)日:2021-07-15

    申请号:US16652180

    申请日:2019-10-18

    Abstract: The present disclosure relates to a gate driving circuit applied to a foldable display panel comprising B display areas arranged in order. The gate driving circuit may include B gate driving subcircuits and a control circuit. Each of the gate driving subcircuits may correspond to one of the display areas and each of the gate driving subcircuits may comprise a plurality of stage gate driving units. The control circuit may be configured to, when the foldable display panel is in a full screen display state, control a type of an input signal in a last stage gate driving unit of a bth gate driving subcircuit to be the same as a type of an input signal in a first stage gate driving unit of a (b+1)th gate driving subcircuit, where B is an integer greater than 1 and b is a positive integer less than B.

    SHIFT REGISTER AND DRIVING METHOD THEREFOR, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

    公开(公告)号:US20180330685A1

    公开(公告)日:2018-11-15

    申请号:US15865550

    申请日:2018-01-09

    Inventor: Can Zheng

    Abstract: Provided is a shift register, comprising an input circuit, an output circuit, and a control circuit, which are electrically connected to a control node. The input circuit is electrically connected with a signal input terminal of the shift register, and is configured to input an input signal provided by the signal input terminal to the control node. The control circuit is electrically connected with a working power supply terminal, and is configured to input an operation voltage provided by the working power supply terminal to the control node. The output circuit is electrically connected with a signal output terminal of the shift register and a clock signal line, and is configured to input one of a voltage of the control node and the first clock signal provided by the clock signal line to the signal output terminal.

    Shift register and a driving method thereof, a gate driving circuit and a display device

    公开(公告)号:US09966957B2

    公开(公告)日:2018-05-08

    申请号:US15519966

    申请日:2016-10-13

    Inventor: Can Zheng Song Song

    CPC classification number: H03K19/096 G09G3/3266 G11C19/184 G11C19/28

    Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register includes a control signal generation module, a first low level pulse generation module, a second low level pulse generation module, and a high level pulse generation module. The control signal generation module generates a first control signal and a second control signal. The first low level pulse generation module receives the first control signal and the second control signal and generate a first low level pulse signal. The second low level pulse generation module receives the first control signal and the second control signal and generate a second low level pulse signal. The high level pulse generation module receives the first control signal and generates a high level pulse signal. This shift register reduces the number of circuit elements.

    Driving method and device for shift register

    公开(公告)号:US11854508B2

    公开(公告)日:2023-12-26

    申请号:US17921082

    申请日:2021-05-12

    CPC classification number: G09G3/3674 G09G2310/0286

    Abstract: A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.

Patent Agency Ranking