公开(公告)号：US11538395B2

公开(公告)日：2022-12-27

申请号：US17256233

申请日：2020-03-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Jiangnan Lu ,  Can Zheng ,  Hao Zhang ,  Long Han ,  Libin Liu ,  Shiming Shi ,  Dawei Wang

IPC: G09G3/20 ,  G11C19/28

Abstract: A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.

公开(公告)号：US11308854B2

公开(公告)日：2022-04-19

申请号：US16642140

申请日：2019-03-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng

IPC: G09G3/20

Abstract: A shift register unit, a driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first input circuit, a second input circuit, an output circuit, a first control circuit, and a second control circuit. The first input circuit is electrically connected to a first node, and is configured to transmit an input signal to the first node; the second input circuit is electrically connected to the first node and a second node, and is configured to control a level of the second node; the first control circuit is electrically connected to the second node and a third node, and is configured to control a level of the third node; and the output circuit is electrically connected to the third node and an output terminal, and is configured to output an output signal to the output terminal.

公开(公告)号：US11232734B2

公开(公告)日：2022-01-25

申请号：US16964465

申请日：2019-09-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Can Zheng ,  Jiangnan Lu ,  Tian Dong ,  Libin Liu ,  Long Han ,  Shiming Shi ,  Dawei Wang

IPC: G09G3/20 ,  G11C19/28

Abstract: A shift register unit, a driving method, a gate driving circuit and a display device are provided. The shift register unit includes a first gate driving output circuit and a second gate driving output circuit. The first gate driving output circuit is used to output a first gate driving signal through the first gate driving signal output terminal; the second gate driving output circuit is used to generate a second gate driving signal outputted simultaneously with the first gate driving signal based on the first gate driving signal, a first clock signal and a second clock signal. In the present disclosure, the second gate driving output circuit is added, the first gate driving signal, the first clock signal, and the second clock signal are used to generate an inverted second gate driving signal, so that positive and negative switching control signals are generated by one stage of shift register unit.

公开(公告)号：US20210217339A1

公开(公告)日：2021-07-15

申请号：US16652180

申请日：2019-10-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng ,  Libin Liu ,  Li Wang ,  Tian Dong ,  Guangliang Shang ,  Xinshe Yin

IPC: G09G3/00

Abstract: The present disclosure relates to a gate driving circuit applied to a foldable display panel comprising B display areas arranged in order. The gate driving circuit may include B gate driving subcircuits and a control circuit. Each of the gate driving subcircuits may correspond to one of the display areas and each of the gate driving subcircuits may comprise a plurality of stage gate driving units. The control circuit may be configured to, when the foldable display panel is in a full screen display state, control a type of an input signal in a last stage gate driving unit of a bth gate driving subcircuit to be the same as a type of an input signal in a first stage gate driving unit of a (b+1)th gate driving subcircuit, where B is an integer greater than 1 and b is a positive integer less than B.

公开(公告)号：US10909920B2

公开(公告)日：2021-02-02

申请号：US16309203

申请日：2018-03-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.

Inventor： Jianchao Zhu ,  Lujiang Huangfu ,  Yunfei Li ,  Can Zheng ,  Libin Liu ,  Yipeng Chen

IPC: G09G3/3233 ,  G09G3/3266

Abstract: A pixel driving circuit and a driving method, and a display device are provided. The driving circuit includes: a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a driving transistor, a sixth switching element, a first storage capacitor and a second storage capacitor.

公开(公告)号：US20180330685A1

公开(公告)日：2018-11-15

申请号：US15865550

申请日：2018-01-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng

IPC: G09G3/36 ,  G09G3/3266

CPC classification number: G09G3/3674 ,  G09G3/3266 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08

Abstract: Provided is a shift register, comprising an input circuit, an output circuit, and a control circuit, which are electrically connected to a control node. The input circuit is electrically connected with a signal input terminal of the shift register, and is configured to input an input signal provided by the signal input terminal to the control node. The control circuit is electrically connected with a working power supply terminal, and is configured to input an operation voltage provided by the working power supply terminal to the control node. The output circuit is electrically connected with a signal output terminal of the shift register and a clock signal line, and is configured to input one of a voltage of the control node and the first clock signal provided by the clock signal line to the signal output terminal.

公开(公告)号：US09966957B2

公开(公告)日：2018-05-08

申请号：US15519966

申请日：2016-10-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Can Zheng ,  Song Song

IPC: G11C19/00 ,  H03K19/096 ,  G11C19/28 ,  G09G3/3266

CPC classification number: H03K19/096 ,  G09G3/3266 ,  G11C19/184 ,  G11C19/28

Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register includes a control signal generation module, a first low level pulse generation module, a second low level pulse generation module, and a high level pulse generation module. The control signal generation module generates a first control signal and a second control signal. The first low level pulse generation module receives the first control signal and the second control signal and generate a first low level pulse signal. The second low level pulse generation module receives the first control signal and the second control signal and generate a second low level pulse signal. The high level pulse generation module receives the first control signal and generates a high level pulse signal. This shift register reduces the number of circuit elements.

公开(公告)号：US12108643B2

公开(公告)日：2024-10-01

申请号：US17953941

申请日：2022-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Guangliang Shang ,  Can Zheng ,  Yu Feng ,  Libin Liu ,  Jie Zhang ,  Mei Li

IPC: H10K59/131 ,  G09G3/3208 ,  H10K59/121

CPC classification number: H10K59/131 ,  H10K59/121 ,  G09G3/3208 ,  G09G2320/0209 ,  G09G2320/0233

Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

公开(公告)号：US11875747B2

公开(公告)日：2024-01-16

申请号：US17793841

申请日：2021-05-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lujiang Huangfu ,  Li Wang ,  Can Zheng ,  Tian Dong ,  Libin Liu

IPC: G09G3/3258 ,  G09G3/3233

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/061 ,  G09G2320/0214 ,  G09G2320/0233 ,  G09G2320/0238 ,  G09G2320/0247 ,  G09G2320/043

Abstract: A pixel driving circuit includes: an energy storage sub-circuit, a reset sub-circuit, a compensation sub-circuit, a driving sub-circuit, and a current leakage suppression sub-circuit. The energy storage sub-circuit is coupled to a first node and a second node. The reset sub-circuit is coupled to the second node, a first scan timing signal terminal, and an initialization signal terminal. The compensation sub-circuit is coupled to the second node, a third node, and a second scan timing signal terminal. The driving sub-circuit is coupled to the second node, the third node, and a first voltage signal terminal. The current leakage suppression sub-circuit is coupled to the energy storage sub-circuit, the reset sub-circuit, and the compensation sub-circuit. The current leakage suppression sub-circuit is configured to suppress current leakage of the energy storage sub-circuit in a process of generating and transmitting the driving signal by the driving sub-circuit.

公开(公告)号：US11854508B2

公开(公告)日：2023-12-26

申请号：US17921082

申请日：2021-05-12

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Tian Dong ,  Shuo Huang ,  Can Zheng

IPC: G09G3/36

CPC classification number: G09G3/3674 ,  G09G2310/0286

Abstract: A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.