Abstract:
The present invention provides a method for designing a mask. First, a main pattern including at least a strip pattern is formed on the mask substrate. A shift feature is added to one end of the strip pattern of the main pattern. Either the phase shift or the optical transmission or both of the shift feature can be adjusted to optimize the resultant critical dimension between line-ends of the main pattern, thus improving pullback of the line-ends of the strip pattern in the main pattern.
Abstract:
An invention of lithography process using an improved reflection mask is provided for extreme ultraviolet (EUV) lithography. In the process an incident EUV is transmitted onto the reflection mask at a grazing incident angle. Therefore a reflected EUV develops a pattern image to a photo resist layer on the surface of the wafer, wherein the shape of the pattern image is dependent on the shape of a plurality of reflective regions on the surface of the reflection mask. Specially, the improved reflection mask is more easily fabricated. The surface roughness and the defects of the reflection mask are also more easily controlled. The improved EUV lithography process is more efficient and cheap.
Abstract:
A photomask with desired illumination conditions can be constructed by combining a base pattern of openings with an assist pattern which includes openings that are offset from respectively corresponding openings of the base pattern by a preset angular distance.
Abstract:
A dual phase shifting mask (PSM)/double exposure lithographic process for manufacturing a shrunk semiconductor device. A semiconductor wafer having a photoresist layer coated thereon is provided. A first phase shift mask is disposed over the semiconductor wafer and implementing a first exposure process to expose the photoresist layer to light transmitted through the first phase shift mask so as to form a latent pattern comprising a peripheral unexposed line pattern in the photoresist layer. The first phase shift mask is then replaced with a second phase shift mask and implementing a second exposure process to expose the photoresist layer to light transmitted through the second phase shift mask so as to remove the peripheral unexposed line pattern.
Abstract:
A method for removing a native oxide layer using hydrogen to react with the native oxide layer is described. Oxygen atoms in silicon dioxide is replaced to achieve the purpose of native oxide removal. Additionally, laser enhancement is used to lower the reaction temperature to between 200°-700° C. The purpose of low-temperature native oxide removal is thus achieved.
Abstract:
The present invention relates to a method of forming a phase shift mask on a mask substrate. This method comprises sequentially forming a phase shifter layer and a shield layer on the mask substrate, forming a photo-resist layer on a predetermined region of the shield layer, wherein the periphery of the photo-resist layer comprises at least one vertical side-wall, and forming a deposition layer uniformly on the photo-resist layer and the shield layer surrounding the photo-resist layer. Next, silylanizing the deposition layer. Next, performing an anisotropic etching process to remove the deposition layer on top of the photo-resist layer and the shield layer surrounding the photo-resist layer, and to partially remove the deposition layer covered on the vertical side-wall of the photo-resist layer so as to form a spacer on the vertical side-wall of the photo-resist layer. Then, vertically removing the shield layer and the phase shifter layer not covered by the photo-resist layer and the spacer, and vertically removing the spacer and the shield layer under the spacer. Lastly, removing the photo-resist layer completely to complete the phase shift mask.
Abstract:
A fabrication method for a vertical MOS device is described, in which dopants are implanted in the active region to form, from the bulk to the surface of the wafer respectively, a first doped layer, a second doped layer and a third doped layer. A portion of the isolation structure above the first doped layer is then removed, exposing the sidewalls of the second doped layer and the surface of the third doped layer but still concealing the first doped layer in the substrate. A gate oxide layer is further formed on the sidewalls of the second doped layer and the surface of the third doped layer. Furthermore, a conductive layer is formed at the second doped layer, covering the isolation structure, wherein the second doped layer and the conductive layer are isolated by the gate oxide layer.
Abstract:
An alignment and exposure process that use the same incident beam. A substrate having a photoresist formed on an upper surface of the substrate is provided. At least one alignment mark is located on a bottom surface of the substrate. A mask is located over the photoresist. An incident beam is projected onto a light splitter over the mask, wherein the incident beam is reflected onto the alignment mark to align the mask with the substrate. The first light is split into a transmission light and a reflection light. The transmission light passes through the light splitter and the mask to expose the photoresist and the reflection light is projected onto the alignment mark to dynamically align the mask with the substrate.
Abstract:
A method of manufacturing a DRAM capacitor comprises the steps of providing a substrate having a word line, a source/drain region, a bit line and a first insulator layer. A hard mask layer and a second insulator layer are formed on the first insulator layer in sequence. Next, an opening is formed to expose a portion of the first insulator layer by patterning the second insulator layer and the hard mask layer. Thereafter, a spacer is formed on the side wall of the opening and a node contact hole is formed to expose a portion of the source/drain region in the first insulator layer. The second insulator layer is stripped to expose the hard mask layer and a conductive layer is formed over the hard mask layer and fills the node contact hole. A bottom electrode is formed by patterning the conductive layer and a dielectric layer and another conductive layer are formed over the bottom electrode in sequence.
Abstract:
An installation for forming a double-sided photomask includes a first and a second particle sources and a first and a second focusing assemblies positioned on each side of a mechanical stage. The mechanical stage is used for holding a masking plate that requires pattern inscription. The particles generated by the first and the second particle sources are channeled to the first and second focusing assemblies, respectively. Within each focusing assembly, the particle beam is focused to a desired resolution for inscribing a pattern onto each face of the masking plate, thereby forming a double-sided photomask. The installation further includes a controlling unit coupled to the particle sources, the focusing assemblies and the mechanical stage for controlling system operation. In addition, there is a photomask pattern generator coupled to the controlling unit for supplying pattern data to the controlling unit.