公开(公告)号：US08329515B2

公开(公告)日：2012-12-11

申请号：US12647888

申请日：2009-12-28

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L21/82

CPC classification number: H01L27/0629 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/5256 ,  H01L29/4925 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.

Abstract translation: 在多晶硅上形成包括一层嵌入硅锗（eSiGe）的栅极堆叠的eFUSE。 一个实施例包括在衬底中形成浅沟槽隔离（STI）区域，在用于PMOS器件的衬底上形成第一栅极堆叠，在用于eFUSE的STI区域上形成第二栅极堆叠，形成第一嵌入硅锗（eSiGe） 在第一栅极堆叠的第一和第二侧上的衬底上，并且在第二栅极堆叠上形成第二eSiGe。 将eSiGe添加到eFUSE栅极堆叠中增加了eFUSE碎片区域和底层金属栅极之间的距离，从而防止了潜在的短路。

公开(公告)号：US08222093B2

公开(公告)日：2012-07-17

申请号：US12707150

申请日：2010-02-17

Applicant: Man Fai Ng ,  Bin Yang

Inventor： Man Fai Ng ,  Bin Yang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/76

CPC classification number: H01L21/84 ,  H01L21/76267 ,  H01L21/823878 ,  H01L29/66772

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract translation: 提供了用于制造在绝缘材料区域内具有阻挡区域的半导体器件的方法和装置，导致从绝缘材料区域的脱气路径。 一种方法包括在靠近半导体材料的隔离区域的绝缘材料内形成阻挡区域，并形成覆盖半导体材料的隔离区域的栅极结构。 阻挡区域与半导体材料的隔离区域相邻，导致绝缘材料内的除气路径。

公开(公告)号：US20110316093A1

公开(公告)日：2011-12-29

申请号：US12821507

申请日：2010-06-23

Applicant: Bin Yang ,  Man Fai NG

Inventor： Bin Yang ,  Man Fai NG

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833

Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

Abstract translation: 短沟道半导体器件形成有与栅电极的底部彼此分离的晕圈。 实施例包括在形成源极/漏极区域和源极/漏极延伸区域之后注入晕圈。 一个实施例包括在衬底中形成源极/漏极延伸区域，在衬底中形成源极/漏极区域，在形成源极漏极区域之后在源极/漏极延伸区域下方形成卤素区域，以及在衬底上形成栅极电极 源/漏区。 通过在涉及源极/漏极和源极/漏极延伸区域的高温处理之后形成晕圈区域，使得光晕扩散最小化，从而在晕圈区域之间保持足够的距离并且减少短沟道NMOS Vt滚降。

公开(公告)号：US20110156146A1

公开(公告)日：2011-06-30

申请号：US12647888

申请日：2009-12-28

Applicant: Bin Yang ,  Man Fai Ng

Inventor： Bin Yang ,  Man Fai Ng

IPC: H01L23/525 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L27/0629 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/5256 ,  H01L29/4925 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.

Abstract translation: 在多晶硅上形成包括一层嵌入硅锗（eSiGe）的栅极堆叠的eFUSE。 一个实施例包括在衬底中形成浅沟槽隔离（STI）区域，在用于PMOS器件的衬底上形成第一栅极堆叠，在用于eFUSE的STI区域上形成第二栅极堆叠，形成第一嵌入硅锗（eSiGe） 在第一栅极堆叠的第一和第二侧上的衬底上，并且在第二栅极堆叠上形成第二eSiGe。 将eSiGe添加到eFUSE栅极堆叠中增加了eFUSE碎片区域和底层金属栅极之间的距离，从而防止了潜在的短路。

公开(公告)号：US20180104815A1

公开(公告)日：2018-04-19

申请号：US15686822

申请日：2017-08-25

Applicant: Bin Yang

Inventor： Bin Yang

IPC: B25J9/08 ,  B25J11/00 ,  B25J19/02

CPC classification number: B25J9/08 ,  B25J9/1617 ,  B25J9/162 ,  B25J11/0085 ,  B25J19/005 ,  B25J19/023 ,  G05B2219/31094 ,  G05B2219/40302 ,  G05B2219/40304 ,  Y02P90/18 ,  Y10S901/01

Abstract: A robot system includes a primary robot frame including a computerized control module providing control commands for the robot system, the primary robot frame including an outer perimeter. The robot system further includes a plurality of submodules, each submodule capable of being selectively docked with the primary robot frame, the submodules each providing different functionality to the robot system. The submodules, when docked with the primary robot frame, fit within the outer perimeter, enabling the robot system to operate in a closed mode, wherein all movement of the robot system is based upon the outer perimeter.

公开(公告)号：US09127088B2

公开(公告)日：2015-09-08

申请号：US13697018

申请日：2011-05-10

Applicant: Richard D. DiMarchi ,  Bin Yang ,  Brian Finan

Inventor： Richard D. DiMarchi ,  Bin Yang ,  Brian Finan

IPC: A61K38/26 ,  C07K14/62 ,  C07K14/72 ,  A61K47/48 ,  C07K14/605

CPC classification number: C07K14/721 ,  A61K38/26 ,  A61K47/55 ,  A61K47/554 ,  A61K47/64 ,  C07K14/605 ,  C07K14/72

Abstract: Provided herein are glucagon superfamily peptides conjugated with NHR ligands that are capable of acting at a nuclear hormone receptor. Also provided herein are pharmaceutical compositions and kits of the conjugates of the invention. Further provided herein are methods of treating a disease, e.g., a metabolic disorder, such as diabetes and obesity, comprising administering the conjugates of the invention.

Abstract translation: 本文提供了与能够作用于核激素受体的NHR配体缀合的胰高血糖素超家族肽。 本文还提供了本发明的缀合物的药物组合物和试剂盒。 本文还提供了治疗疾病，例如代谢紊乱（例如糖尿病和肥胖症）的方法，其包括施用本发明的缀合物。

公开(公告)号：US09111341B2

公开(公告)日：2015-08-18

申请号：US13997258

申请日：2011-12-23

Applicant: Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

Inventor： Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

IPC: G06K9/00 ,  G06T1/00 ,  G06K9/34

CPC classification number: G06T1/0021 ,  G06K9/348 ,  G06K2209/01 ,  G06T2201/0051 ,  G06T2201/0062 ,  G06T2201/0083

Abstract: The application provides a method for partitioning a watermark image with western language characters, comprising: partitioning a western language characters image along rows and columns to form a plurality of character image blocks; identifying valid character image blocks from the formed character image blocks; counting sizes of the valid character image blocks to determine if the image corresponds to a document with a large font size or a document with a small font size; dividing words in the image into a plurality of groups, wherein each divided group in the document with large font size has different numbers of words from that with small font size; and dividing equally the divided word groups into multiple portions corresponding to watermark image blocks. The application further provides a device for partitioning a watermark image with western language characters. The operability of watermark embedding process can be ensured through the above technical solution.

Abstract translation: 该应用程序提供了一种用于用西方语言字符分割水印图像的方法，包括：沿着行和列划分西方语言字符图像以形成多个字符图像块; 从形成的字符图像块中识别有效的字符图像块; 计算有效字符图像块的大小，以确定图像是否对应于具有较大字体大小的文档或具有小字体大小的文档; 将图像中的单词划分成多个组，其中具有大字体大小的文档中的每个划分组具有与具有小字体尺寸的单词不同的字数; 并将划分的字组分成相当于水印图像块的多个部分。 该应用还提供了一种用于用西语字符分割水印图像的设备。 通过上述技术方案可以确保水印嵌入过程的可操作性。

公开(公告)号：US08980830B2

公开(公告)日：2015-03-17

申请号：US12740206

申请日：2008-10-27

Applicant: Richard D. Dimarchi ,  Bin Yang ,  Chenguang Ouyang

Inventor： Richard D. Dimarchi ,  Bin Yang ,  Chenguang Ouyang

IPC: C07K14/605 ,  C07K7/02 ,  A61K38/26 ,  A61K38/16 ,  A61K38/22 ,  A61P3/04 ,  A61P3/10 ,  A61K38/00

CPC classification number: C07K14/605 ,  A61K38/00 ,  A61K38/16 ,  A61K38/22 ,  A61K38/26 ,  C07K7/02

Abstract: Glucagon analogs are disclosed that exhibit both glucagon antagonist and GLP-1 agonist activity. In one embodiment, the glucagon antagonist/GLP-1 agonist comprises a modified amino acid sequence of native glucagon, in which the first one to five N-terminal amino acids of native glucagon is deleted and in which the alpha helix is stabilized.

Abstract translation: 公开了显示胰高血糖素拮抗剂和GLP-1激动剂活性的胰高血糖素类似物。 在一个实施方案中，胰高血糖素拮抗剂/ GLP-1激动剂包含天然胰高血糖素的修饰的氨基酸序列，其中天然胰高血糖素的前一至五个N-末端氨基酸被缺失，并且其中α螺旋被稳定。

公开(公告)号：US20140055152A1

公开(公告)日：2014-02-27

申请号：US13594292

申请日：2012-08-24

Applicant: Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

Inventor： Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

IPC: G01R27/08

CPC classification number: G01R27/08 ,  G01R31/2831 ,  H01L22/14 ,  H01L22/20

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract translation: 描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。 还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

公开(公告)号：US20140033937A1

公开(公告)日：2014-02-06

申请号：US13996967

申请日：2011-12-24

Applicant: Haifeng Li ,  Bin Yang

Inventor： Haifeng Li ,  Bin Yang

IPC: G03F5/20

CPC classification number: G03F5/20 ,  H04N1/4055

Abstract: The present application provides a screen method for intaglio printing, comprising: dividing multiple classes of regions according to a brightness range; and generating screen dots with various screen patterns for the grouped classes of regions. The present application also provides a screen device for intaglio printing, comprising: a dividing module configured to group multiple classes of regions according to the brightness range; and a generating module configured to generate screen dots with various screen patterns for the grouped classes of regions. Since multiple kinds of screen patterns are applied in the technical solutions in present application, the problem, i.e., water ripple will occur in the prior art, may be addressed, so as to improve the quality of printing.

Abstract translation: 本申请提供了一种用于凹版印刷的屏幕方法，包括：根据亮度范围划分多个类别的区域; 并且为分组的区域类别生成具有各种屏幕图案的屏幕点。 本申请还提供了一种用于凹版印刷的屏幕装置，包括：分割模块，被配置为根据亮度范围对多个类别的区域进行分组; 以及生成模块，被配置为生成用于所述分组的区域类别的各种屏幕图案的屏幕点。 由于在本申请中的技术方案中应用了多种屏幕图案，所以可以解决现有技术中出现的水波纹问题，以提高打印质量。