摘要:
Combinatorial processing of a substrate comprising site-isolated sputter deposition and site-isolated plasma etching can be performed in a same process chamber. The process chamber, configured to carry out sputter deposition and RF plasma etch, comprises a grounded shield having at least an aperture disposed above the substrate to form a small, dark space gap to reduce or eliminate any plasma formation within the gap
摘要:
Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.
摘要:
A shield for a DC magnetron sputtering reactor, particularly advantageous for reliably igniting the plasma used in sputtering a ferromagnetic material such as cobalt or nickel. The grounded shield includes a slanted portion separated from the beveled periphery of the target by a small gap operating as a dark space. The shield also includes a straight cylindrical portion surrounding the main processing area. The slanted portion is joined to the cylindrical portion at a knee According to one embodiment of the invention, the knee is located greater than 9 mm from the face of the target and at a radial position at least 1 mm inward of the outer periphery of the target face.
摘要:
A method of cleaning a contact area of a semiconductor or metal region on a substrate of an electronic device. First, the contact area is cleaned by exposing the substrate to a plasma that includes fluorine-containing species. Second, the substrate is exposed to a second atmosphere that scavenges fluorine, preferably formed by plasma decomposition of a hydrogen-containing gas. The second atmosphere removes any fluorine residue remaining on the contact area and overcomes any need to include argon sputtering in the cleaning process. Another aspect of the invention is a method of depositing a refractory metal over a contact area of a semiconductor region on a substrate. The contact area is cleaned according to the two-step process of the preceding paragraph. Then a refractory metal is deposited over the contact area. The two-step cleaning process can reduce the electrical resistance between the refractory metal and the semiconductor region. Furthermore, if the substrate is annealed to interdiffuse atoms of the semiconductor material and the refractory metal, the two-step cleaning process can reduce the anneal temperature required to achieve a desired low electrical resistance.
摘要:
We have discovered particular wetting layer or wetting/barrier layer structures which enable depositing of overlying aluminum interconnect layers having texturing sufficient to provide a Rocking Curve FWHM angle &thgr; of about 1° or less. The aluminum interconnect layer exhibiting a Rocking Curve FWHM angle &thgr; of about 1° or less exhibits excellent electromigration properties. In addition when the aluminum layer is subsequently pattern etched, the sidewalls of the etched aluminum pattern exhibit a surprising reduction in pitting compared with pattern etched aluminum layers exhibiting higher Rocking Curve FWHM angles.
摘要:
Native oxides can be removed from a substrate having high aspect ratio openings therein by using a plasma gas precursor mixture of a reactive halogen-containing gas and a carrier gas such as helium. The lightweight ions generated in the plasma react with oxygen to produce very volatile oxygen-containing species that can be readily removed through the exhaust system of the plasma chamber, preventing re-deposition of oxides on the surface of the substrate or on the sidewalls or bottom of the openings. When the substrate is mounted in a plasma chamber having dual power sources that can form a plasma above the substrate and can apply bias to the substrate, tapered openings are formed rapidly that can be readily filled without forming voids.
摘要:
Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.