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公开(公告)号：US20210223871A1
公开(公告)日：2021-07-22
申请号：US16301843
申请日：2018-04-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Seungwoo Han
Abstract: The present disclosure is related to a flexible display panel. The flexible display panel may include a display substrate, a plurality of pixel units arranged in an array on the display substrate, and at least a strain sensor on the display substrate. The strain sensor may be arranged corresponding to a region comprising at least one of the plurality of pixel units. The strain sensor may be configured to detect deformation in the region comprising at least one of the plurality of pixel units and to generate a detection signal.
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12.发明授权公开(公告)号：US10811114B2
公开(公告)日：2020-10-20
申请号：US16138878
申请日：2018-09-21
Applicant: BOE Technology Group Co., Ltd.
Inventor： Lijun Yuan , Mingfu Han , Seung Woo Han , Xing Yao , Zhichong Wang , Guangliang Shang , Haoliang Zheng
IPC: G11C19/00 , G11C19/28 , G09G3/3258 , G09G3/36
Abstract: Embodiments of the present application provide a shift register unit, a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit comprises at least two sub-circuits of a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit. The first output sub-circuit is configured to output a voltage at a signal output terminal to a reset signal output terminal; the second output sub-circuit is configured to output the voltage at the signal output terminal to a gating signal output terminal; and the third output sub-circuit is configured to output a voltage at a second voltage terminal to a light-emitting control signal output terminal or is configured to output a voltage at a first voltage terminal to the light-emitting control signal output terminal.
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13.发明申请公开(公告)号：US20190221178A1
公开(公告)日：2019-07-18
申请号：US15574867
申请日：2017-05-17
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Seungwoo Han , Guangliang Shang
IPC: G09G3/36
CPC classification number: G09G3/3614 , G02F1/13624 , G09G3/20 , G09G3/34 , G09G3/36 , G09G2300/0814 , G09G2300/0823 , G09G2310/061 , G09G2320/045 , H01L27/1225
Abstract: A pixel driving circuit for a display apparatus. The pixel driving circuit may include a first gate line, a second gate line, a data line, a first thin-film transistor, and a second thin-film transistor. A gate of the first thin-film transistor may be coupled to the first gate line. A source of the first thin-film transistor may be coupled to the data line. A drain of the first thin-film transistor may be coupled to a source of the second thin-film transistor. A gate of the second thin-film transistor may be coupled to the second gate line. A drain of the second thin-film transistor may be coupled to a pixel electrode.
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14.发明授权公开(公告)号：US10217391B2
公开(公告)日：2019-02-26
申请号：US15541639
申请日：2016-09-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Xing Yao , Seungwoo Han , Yujie Gao , Yuanbo Zhang , Ming Chen , Jungmok Jun , Xue Dong
IPC: G11C19/28 , G09G3/32 , G09G3/36 , G09G3/20 , G09G3/3266
Abstract: Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.
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公开(公告)号：US10204695B2
公开(公告)日：2019-02-12
申请号：US15520191
申请日：2016-11-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Seungwoo Han , Mingfu Han , Haoliang Zheng , Xing Yao , Hyunsic Choi
Abstract: The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.
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Patent Agency Ranking
公开(公告)号：US10192504B2
公开(公告)日：2019-01-29
申请号：US15501265
申请日：2016-07-01
Applicant: BOE TECHNOLOGY GROUP CO., LTD
Inventor： Mingfu Han , Seungwoo Han , Guangliang Shang , Hyunsic Choi , Xing Yao , Haoliang Zheng , Xue Dong , Jungmok Jun , Yunsik Im
Abstract: The present disclosure provides a shift register, including: an input unit, an output control unit, a first pull-down unit, a second pull-down unit, a reset unit, and a pull-down control unit. The input unit comprises a control terminal connected to a signal input terminal, a first terminal connected to a first voltage terminal, and a second terminal connected to a first node. The output control unit comprises a control terminal connected to the first node, a first terminal connected to a first clock signal terminal, and a second terminal connected to a signal output terminal. The first pull-down unit comprises a control terminal connected to a second node, a first terminal connected to the first node, and a second terminal connected to a compensation signal terminal. The second pull-down unit comprises a control terminal connected to the compensation signal terminal, and a first terminal connected to the second node.
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公开(公告)号：US10115335B2
公开(公告)日：2018-10-30
申请号：US15502983
申请日：2016-05-19
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Haoliang Zheng , Seungwoo Han , Guangliang Shang , Hyunsic Choi , Mingfu Han , Xing Yao , Zhichong Wang , Lijun Yuan
Abstract: The present disclosure relates to a shift register unit and driving method thereof, a gate driving circuit and a display device. The shift register unit comprises: an input module for controlling a level of a first node based on a scan pulse, an output module for controlling a scan pulse output based on the level of the first node, a reset module for resetting the first node and the scan pulse output, and a control module for generating a reset trigger signal, wherein the reset module further resets the first node based on the reset trigger signal. The shift register units can be cascaded to form a gate driving circuit to realize output of multiple scan pulses. By integrating such a gate driving circuit on the array substrate, area of the bezel region of the array substrate can be reduced, thereby facilitating bezel narrowing of a display device. At the same time, due to presence of the control module, the reset module is enabled to reset the first node more stably while normal output of the scan pulse is maintained.
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公开(公告)号：US20180226039A1
公开(公告)日：2018-08-09
申请号：US15542365
申请日：2016-12-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Seung Woo Han , Guangliang Shang
CPC classification number: G09G3/3677 , G09G3/3648 , G09G2310/0286 , G11C19/28
Abstract: A shift register unit, gate driving device, display device and driving method are provided. The shift register unit includes: an input circuit, configured to control a potential of a pull-up control node based on an input signal; a pull-down control circuit, configured to control a potential of a pull-down control node based on the input signal and the potential of the pull-up control node when first signal is at a first level; a pull-down circuit, configured to pull down the potential of the pull-up control node based on the potential of the pull-down control node; a pull-up circuit, configured to control an output signal output from a signal output terminal based on the potential of the pull-up control node and the clock signal; and a reset circuit, configured to reset the output signal based on the potential of the pull-down control node when second signal is at a second level.
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19.发明申请公开(公告)号：US20180204494A1
公开(公告)日：2018-07-19
申请号：US15541639
申请日：2016-09-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Xing Yao , Seungwoo Han , Yujie Gao , Yuanbo Zhang , Ming Chen , Jungmok Jun , Xue Dong
CPC classification number: G09G3/20 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G11C19/28 , G11C19/287
Abstract: Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.
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20.发明授权公开(公告)号：US09818883B2
公开(公告)日：2017-11-14
申请号：US14785606
申请日：2015-04-14
Applicant: Boe Technology Group Co., Ltd.
Inventor： Guangliang Shang
IPC: H01L29/786 , H01L27/12 , H01L29/66
CPC classification number: H01L29/78696 , H01L27/12 , H01L29/66742 , H01L29/66969 , H01L29/786 , H01L29/7869
Abstract: A metal oxide thin film transistor and a preparation method thereof, as well as an array substrate, wherein the metal oxide thin film transistor comprises a base substrate, an active layer and a source-drain metal layer formed on the base substrate that contact each other and are located in different layers, the source-drain metal layer comprising separated source electrode and drain electrode; the active layer having a hollow structure in a channel area located between the source electrode and the drain electrode.
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