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公开(公告)号：US11809048B2
公开(公告)日：2023-11-07
申请号：US17475045
申请日：2021-09-14
发明人： Hyunsic Choi
IPC分类号： G02F1/1343 , G02F1/1362
CPC分类号： G02F1/134309 , G02F1/13439 , G02F1/136286
摘要： The present disclosure discloses an array substrate, a liquid crystal display panel and a display device. The array substrate includes: a base substrate, and a first electrode and a second electrode located in a region defined by intersection of two adjacent data lines, a gate line and a common electrode signal line, where the second electrode is located on a side of the first electrode facing away from the base substrate; the first electrode is in a block shape; the second electrode has a symmetry axis perpendicular to the gate line and passing through the center of the second electrode; the second electrode includes: a frame with an opening in a side; an opening side of the frame faces a first type of signal lines; the first type of signal lines are other signal lines than the data lines and signal lines parallel to the data lines.
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公开(公告)号：US10558073B2
公开(公告)日：2020-02-11
申请号：US15565374
申请日：2016-11-04
发明人： Hui Li , Hyunsic Choi , Jing Lv , Xue Dong
IPC分类号： G02F1/1335 , G02F1/1343 , G02F1/1362
摘要： The present application discloses a liquid crystal display panel including an array substrate having a data line layer including a plurality of columns of data lines; a counter substrate facing the array substrate, including a base substrate and a conductive material layer on the base substrate having a plurality of conductive material columns for preventing light leakage; and a black matrix layer having a plurality of black matrix columns corresponding to the plurality of conductive material columns and the plurality of columns of data lines.
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公开(公告)号：US20190250455A1
公开(公告)日：2019-08-15
申请号：US16242261
申请日：2019-01-08
发明人： Yunsik Im , Yoonsung Um , Liwei Liu , Feng Liao , Hui Zhang , Yunyun Tian , Hyunsic Choi
IPC分类号： G02F1/1335 , G02F1/1343 , G02F1/1362
CPC分类号： G02F1/133528 , G02F1/134309 , G02F1/136209 , G02F2001/133548 , G02F2001/136222
摘要： The present disclosure provides a display panel, a manufacturing method thereof and a display device. The display panel includes: a first substrate and a second substrate arranged opposite to each other, a liquid crystal layer arranged between the first substrate and the second substrate; and a first polarizer arranged between the first substrate and the liquid crystal layer. Liquid crystal molecules in the liquid crystal layer are initially aligned without an alignment film.
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4.发明申请公开(公告)号：US20180301200A1
公开(公告)日：2018-10-18
申请号：US15520191
申请日：2016-11-04
发明人： Guangliang Shang , Seungwoo Han , Mingfu Han , Haoliang Zheng , Xing Yao , Hyunsic Choi
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3677 , G09G2310/0286 , G09G2310/06 , G09G2310/08 , G09G2330/06
摘要： The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.
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公开(公告)号：US10096374B2
公开(公告)日：2018-10-09
申请号：US15539220
申请日：2016-11-01
发明人： Guangliang Shang , Seungwoo Han , Haoliang Zheng , Xing Yao , Mingfu Han , Hyunsic Choi , Yunsik Im , Yinglong Huang , Jungmok Jun , Xue Dong
摘要： The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.
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公开(公告)号：US10002675B2
公开(公告)日：2018-06-19
申请号：US15504119
申请日：2016-08-12
发明人： Haoliang Zheng , Seungwoo Han , Xing Yao , Hyunsic Choi , Guangliang Shang , Mingfu Han , Yunsik Im , Jungmok Jun , Xue Dong
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3677 , G09G3/3688 , G09G2310/0267 , G09G2310/0286 , G11C19/184 , H01L27/1222 , H01L27/124 , H01L27/1251
摘要： The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.
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7.发明授权公开(公告)号：US09341880B2
公开(公告)日：2016-05-17
申请号：US14395650
申请日：2013-12-25
发明人： Qiangtao Wang , Hyunsic Choi , Zheng Fang , Yoonsung Um
IPC分类号： G09G3/36 , G02F1/1335 , G02F1/1343 , G09G3/20 , G02F1/1362
CPC分类号： G02F1/133514 , G02F1/133512 , G02F1/134336 , G02F1/136286 , G02F2001/134345 , G02F2201/40 , G09G3/2003 , G09G3/3607 , G09G3/3614 , G09G3/3648 , G09G2300/08 , G09G2320/0233
摘要： In a liquid crystal display panel, as the arrangement of the color filters of the sub-pixel units of every two adjacent pixel units in the row direction, from at least one group composed of two adjacent columns of pixel units in the row direction, is changed, the color filters of two adjacent sub-pixel units in the row direction, which belong to different two pixel units, have the same color; position of the data line connected with the sub-pixel units with color filters of the same color is changed, so that the data line is provided at a side of one of the sub-pixel units with color filters of the same color far away from the other one thereof. Therefore, while the color mixing phenomenon is avoided, a part of the black matrix, which should be provided between the two adjacent sub-pixel units in the row direction, may be omitted.
摘要翻译： 在液晶显示面板中，作为行方向上每两个相邻像素单元的子像素单元的滤色器的排列，从由行方向上的两个相邻列的像素单元构成的至少一个组为 属于不同的两个像素单元的行方向上的两个相邻子像素单元的滤色器具有相同的颜色; 与具有相同颜色的滤色器的子像素单元连接的数据线的位置被改变，使得数据线被设置在具有相同颜色的滤色器的一个子像素单元的一侧，其颜色远离 另一个。 因此，在避免混色现象的情况下，可以省略在行方向上在两个相邻的子像素单元之间设置的黑矩阵的一部分。
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公开(公告)号：US11668986B2
公开(公告)日：2023-06-06
申请号：US17582525
申请日：2022-01-24
发明人： Zheng Fang , Pengxia Liang , Ge Shi , Song Yang , Yujie Liu , Jiahui Han , Yanliu Sun , Hyunsic Choi , Hongpeng Li
IPC分类号： G02F1/1362
CPC分类号： G02F1/136286 , G02F1/136277
摘要： An array substrate is provided. One of a first electrode layer and a second electrode layer in the array substrate includes at least one slit electrode. The slit electrode is disposed between two adjacent data leads in the array substrate, and includes an electrode connecting portion and a plurality of first strip-shaped sub-electrodes. The electrode connecting portion includes a first connecting section parallel to and adjacent to the data lead. A width of the first strip-shaped sub-electrode gradually decreases along a direction going away from the first strip-shaped sub-electrode, and a distance between two adjacent first strip-shaped sub-electrodes in a direction parallel to an extending direction of the first connecting section gradually increases along the direction going away from the first connecting section.
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公开(公告)号：US10283039B2
公开(公告)日：2019-05-07
申请号：US15529731
申请日：2016-11-04
发明人： Hyunsic Choi , Seungwoo Han
摘要： The present application discloses an N-th shift register unit circuit including at least a gate-drive signal output sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit respectively connected between a pull-up node and a pull-down node and provided with a p-th clock signal in addition to an n-th clock signal. A driving method includes controlling the pull-down node at turn-off voltage level when the p-th clock signal is at turn-on voltage level during which the n-th clock signal is correspondingly rising to turn-on voltage level from turn-off voltage level.
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公开(公告)号：US09804453B2
公开(公告)日：2017-10-31
申请号：US14422749
申请日：2014-04-25
发明人： Hyunsic Choi , Heecheol Kim
IPC分类号： G02F1/1343 , G02F1/1333 , G02F1/1335 , G02F1/1368 , G02F1/1339 , G02F1/1362
CPC分类号： G02F1/134363 , G02F1/133345 , G02F1/133512 , G02F1/133514 , G02F1/1339 , G02F1/134309 , G02F1/1368 , G02F2001/13398 , G02F2001/134381 , G02F2001/136222 , G02F2201/121 , G02F2202/16
摘要： The embodiment of the present invention discloses a display device, which relates to the field of display, may realize low-frequency (low-standing-wave) driving and may prevent the aperture ratio from being reduced as a result of ensuring the charge rate during high-frequency driving. The display device provided by the present invention comprises a first substrate and a second substrate which are assembled with each other to form a cell, wherein the first substrate comprises a first electrode layer, the second substrate comprises a second electrode layer, the first substrate further comprises a third electrode layer arranged on one side, far from the second substrate, of the first electrode layer, and an insulation layer is arranged between the third electrode layer; and the first electrode layer, and the third electrode layer is electrically connected with the second electrode layer. The display device is suitable for being driven at low frequency.
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